EP1800GC-2 datasheet, PDF - EEWORLD Datasheet

EP1800GC-2: DescriptionUV PLD, 70ns, 48-Cell, CMOS, CPGA68, WINDOWED, CERAMIC, PGA-68; CategoryProgrammable logic devices Programmable logic; File Size611KB，11 Pages; ManufacturerAltera (Intel)

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EP1800GC-2 Overview

UV PLD, 70ns, 48-Cell, CMOS, CPGA68, WINDOWED, CERAMIC, PGA-68

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Altera (Intel)
Parts packaging code	PGA
package instruction	WPGA, PGA68,11X11
Contacts	68
Reach Compliance Code	unknown
Other features	48 MACROCELLS
maximum clock frequency	20.8 MHz
In-system programmable	NO
JESD-30 code	S-CPGA-P68
JESD-609 code	e0
JTAG BST	NO
length	27.94 mm
Humidity sensitivity level	1
Dedicated input times	12
Number of I/O lines	48
Number of macro cells	48
Number of terminals	68
Maximum operating temperature	70 °C
Minimum operating temperature
organize	12 DEDICATED INPUTS, 48 I/O
Output function	MACROCELL
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	WPGA
Encapsulate equivalent code	PGA68,11X11
Package shape	SQUARE
Package form	GRID ARRAY, WINDOW
Peak Reflow Temperature (Celsius)	220
power supply	5 V
Programmable logic type	UV PLD
propagation delay	70 ns
Certification status	Not Qualified
Maximum seat height	5.0038 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
Maximum time at peak reflow temperature	30
width	27.94 mm

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