LF43168GC15 datasheet, PDF - EEWORLD Datasheet

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LF43168GC15: DescriptionDigital Filter, 10-Bit, CMOS, CPGA84, CERAMIC, PGA-84; CategoryThe embedded processor and controller Microcontrollers and processors; File Size293KB，16 Pages; ManufacturerLOGIC Devices; Websitehttp://www.logicdevices.com/

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LF43168GC15 Overview

Digital Filter, 10-Bit, CMOS, CPGA84, CERAMIC, PGA-84

LF43168GC15 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	LOGIC Devices
Parts packaging code	PGA
package instruction	PGA, PGA84M,11X11
Contacts	84
Reach Compliance Code	unknown
ECCN code	3A001.A.3
Other features	2 X 10 BIT DATA INPUT BUS; ICC SPECIFIED @ 20MHZ
boundary scan	NO
maximum clock frequency	66.7 MHz
External data bus width	10
JESD-30 code	S-CPGA-P84
JESD-609 code	e0
length	29.464 mm
low power mode	NO
Humidity sensitivity level	3
Number of terminals	84
Maximum operating temperature	70 °C
Minimum operating temperature
Output data bus width	28
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Encapsulate equivalent code	PGA84M,11X11
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	225
power supply	5 V
Certification status	Not Qualified
Maximum seat height	4.445 mm
Maximum slew rate	300 mA
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
Maximum time at peak reflow temperature	NOT SPECIFIED
width	29.464 mm
uPs/uCs/peripheral integrated circuit type	DSP PERIPHERAL, DIGITAL FILTER

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LF43168

DEVICES INCORPORATED

Dual 8-Tap FIR Filter

LF43168

DEVICES INCORPORATED

Dual 8-Tap FIR Filter

DESCRIPTION

The

LF43168

is a high-speed dual FIR

filter capable of filtering data at real-

time video rates. The device contains

two FIR filters which may be used as

two separate filters or cascaded to

form one filter. The input and coeffi-

cient data are both 10-bits and can be

in unsigned, two’s complement, or

mixed mode format.

The filter architecture is optimized for

symmetric coefficient sets. When

symmetric coefficient sets are used,

each filter can be configured as an 8-tap

FIR filter. If the two filters are cas-

caded, a 16-tap FIR filter can be

implemented. When asymmetric

coefficient sets are used, each filter is

configured as a 4-tap FIR filter. If both

filters are cascaded, an 8-tap filter can

be implemented. The LF43168 can

decimate the output data by as much

as 16:1. When the device is pro-

grammed to decimate, the number of

clock cycles available to calculate filter

taps increases. When configured for

16:1 decimation, each filter can be

configured as a 128-tap FIR filter (if

symmetric coefficient sets are used).

By cascading these two filters, the

device can be configured as a 256-tap

FIR filter.

There is on-chip storage for 32

different sets of coefficients. Each set

consists of eight coefficients. Access

to more than one coefficient set

facilitates adaptive filtering opera-

tions. The 28-bit filter output can be

rounded from 8 to 19 bits.

FEATURES

66 MHz Data and Computation Rate

Two Independent 8-Tap or Single

16-Tap FIR Filters

10-bit Data and Coefficient Inputs

32 Programmable Coefficient Sets

Supports Interleaved Coefficient Sets

User Programmable Decimation up

to 16:1

Maximum of 256 FIR Filter Taps,

16 x 16 2-D Kernels, or 10 x 20-bit

Data and Coefficients

Replaces Harris HSP43168

Package Styles Available:

• 84-pin Plastic LCC, J-Lead

• 100-pin Plastic Quad Flatpack

• 84-pin Ceramic PGA

LF43168 B

LOCK

IAGRAM

INB

9-0

OUT

8-0

MUX

INA

9-0

CSEL

4-0

CIN

9-0

8-0

COEFFICIENT

BANK A

FILTER

CELL A

MUX

COEFFICIENT

BANK B

FILTER

CELL B

CONTROL

MUX/ADDER

OUT

27-9

OEL

OEH

Video Imaging Products

03/22/1999–LDS.43168-G

LF43168GC15 Related Products

	LF43168GC15	LF43168JC15	LF43168JC30	LF43168GC22
Description	Digital Filter, 10-Bit, CMOS, CPGA84, CERAMIC, PGA-84	Digital Filter, 10-Bit, CMOS, PQCC84, PLASTIC, LCC-84	Digital Filter, 10-Bit, CMOS, PQCC84, PLASTIC, LCC-84	Digital Filter, 10-Bit, CMOS, CPGA84, CERAMIC, PGA-84
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible
Maker	LOGIC Devices	LOGIC Devices	LOGIC Devices	LOGIC Devices
Parts packaging code	PGA	LCC	LCC	PGA
package instruction	PGA, PGA84M,11X11	QCCJ, LDCC84,1.2SQ	QCCJ, LDCC84,1.2SQ	PGA, PGA84M,11X11
Contacts	84	84	84	84
Reach Compliance Code	unknown	compli	compli	unknown
ECCN code	3A001.A.3	3A001.A.3	3A991.A.2	3A001.A.3
Other features	2 X 10 BIT DATA INPUT BUS; ICC SPECIFIED @ 20MHZ	2 X 10 BIT DATA INPUT BUS; ICC SPECIFIED AT 20MHZ	2 X 10 BIT DATA INPUT BUS; ICC SPECIFIED AT 20MHZ	2 X 10 BIT DATA INPUT BUS; ICC SPECIFIED @ 20MHZ
boundary scan	NO	NO	NO	NO
maximum clock frequency	66.7 MHz	66.66 MHz	33.33 MHz	45.45 MHz
External data bus width	10	10	10	10
JESD-30 code	S-CPGA-P84	S-PQCC-J84	S-PQCC-J84	S-CPGA-P84
JESD-609 code	e0	e0	e0	e0
length	29.464 mm	29.3116 mm	29.3116 mm	29.464 mm
low power mode	NO	NO	NO	NO
Humidity sensitivity level	3	3	3	3
Number of terminals	84	84	84	84
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C
Output data bus width	28	28	28	28
Package body material	CERAMIC, METAL-SEALED COFIRED	PLASTIC/EPOXY	PLASTIC/EPOXY	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA	QCCJ	QCCJ	PGA
Encapsulate equivalent code	PGA84M,11X11	LDCC84,1.2SQ	LDCC84,1.2SQ	PGA84M,11X11
Package shape	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY	CHIP CARRIER	CHIP CARRIER	GRID ARRAY
Peak Reflow Temperature (Celsius)	225	NOT SPECIFIED	NOT SPECIFIED	225
power supply	5 V	5 V	5 V	5 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	4.445 mm	5.08 mm	5.08 mm	4.445 mm
Maximum slew rate	300 mA	300 mA	300 mA	300 mA
Maximum supply voltage	5.25 V	5.25 V	5.25 V	5.25 V
Minimum supply voltage	4.75 V	4.75 V	4.75 V	4.75 V
Nominal supply voltage	5 V	5 V	5 V	5 V
surface mount	NO	YES	YES	NO
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	PIN/PEG	J BEND	J BEND	PIN/PEG
Terminal pitch	2.54 mm	1.27 mm	1.27 mm	2.54 mm
Terminal location	PERPENDICULAR	QUAD	QUAD	PERPENDICULAR
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	29.464 mm	29.3116 mm	29.3116 mm	29.464 mm
uPs/uCs/peripheral integrated circuit type	DSP PERIPHERAL, DIGITAL FILTER	DSP PERIPHERAL, DIGITAL FILTER	DSP PERIPHERAL, DIGITAL FILTER	DSP PERIPHERAL, DIGITAL FILTER

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