1CY 7C47 4
CY7C470
CY7C472
CY7C474
8K x 9 FIFO, 16K x 9 FIFO
32K x 9 FIFO with Programmable Flags
Features
• 8K x 9, 16K x 9, and 32K x 9 FIFO buffer memory
• Asynchronous read/write
• High-speed 33.3-MHz read/write independent of
depth/width
• Low operating power
— I
CC
(max.) = 70 mA
• Programmable Almost Full/Empty flag
• Empty, Almost Empty, Half Full, Almost Full, and Full
status flags
• Programmable retransmit
• Expandable in width
•
5V
±
10% supply
• TTL compatible
• Three-state outputs
• Proprietary 0.8-micron CMOS technology
offered in 600-mil DIP, PLCC, and LCC packages. Each FIFO
memory is organized such that the data is read in the same
sequential order that it was written. Three status pins—Emp-
ty/Full (E/F), Programmable Almost Full/Empty (PAFE), and
Half Full (HF)—are provided to the user. These pins are de-
coded to determine one of six states: Empty, Almost Empty,
Less than Half Full, Greater than Half Full, Almost Full, and
Full.
The read and write operations may be asynchronous; each
can occur at a rate of 33.3 MHz. The write operation occurs
when the write (W) signal goes LOW. Read occurs when read
(R) goes LOW. The nine data outputs go into a high-imped-
ance state when R is HIGH.
The user can store the value of the read pointer for retransmit
by using the MARK pin. A LOW on the retransmit (RT) input
causes the FIFO to resend data by resetting the read pointer
to the value stored in the mark pointer.
In the standalone and width expansion configurations, a LOW
on the retransmit (RT) input causes the FIFO to resend the
data. With the mark feature, retransmit can start from any word
in the FIFO.
The CYC47X series is fabricated using a proprietary 0.8-mi-
cron N-well CMOS technology. Input ESD protection is greater
than 2001V and latch-up is prevented by the use of reliable
layout techniques, guard rings, and a substrate bias generator.
Functional Description
The CYC47X FIFO series consists of high-speed, low-power,
first-in first-out (FIFO) memories with programmable flags and
retransmit mark. The CY7C470, CY7C472, and CY7C474 are
8K, 16K, and 32K words by 9 bits wide, respectively. They are
Logic Block Diagram
DATAINPUTS
(D
0
–D
8
)
Pin Configurations
PLCC/LCC
Top View
W
4
PROGRAMMABLE
FLAG REGISTER
D
2
D
1
D
0
MARK
FLAG
LOGIC
HF
E/F
PAFE
R
RT
MARK
PAFE
Q
0
Q
1
NC
Q
2
5
6
7
8
9
10
11
12
7C470
7C472
7C474
3
2
1
32 31 30
29
28
27
26
25
24
23
22
D
8
D
6
D
7
NC
RT
MR
E/F
HF
Q
7
Q
6
D
3
D
2
D
1
D
0
MARK
PAFE
Q
0
Q
1
Q
2
Q
3
Q
8
GND
MARK
POINTER
7C470–2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
7C470
7C472
7C474
DIP
Top View
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
cc
D
4
D
5
D
6
D
7
RT
MR
E/F
HF
Q
7
Q
6
Q
5
Q
4
R
W
WRITE
POINTER
RAM ARRAY
8K x 9
16K x 9
32K x 9
READ
POINTER
13
21
14 15 16 17 18 19 20
7C470–3
THREE–
STATE
BUFFERS
DATAOUTPUTS
(Q
0
–Q
8
)
RESET
LOGIC
MR
7C470–1
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
• CA 95134 •
408-943-2600
December 1990 – Revised April 1995
CY7C470
CY7C472
CY7C474
Selection Guide
7C470–15
7C472–15
7C474–15
Frequency (MHz)
Maximum Access Time (ns)
Maximum Operating Current (mA)
Commercial
Military/Industrial
33.3
15
105
7C470–20
7C472–20
7C474–20
33.3
20
7C470–25
7C472–25
7C474–25
28.5
25
7C470–40
7C472–40
7C474–40
20
40
Maximum Ratings
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ............................................... –0.5V to +7.0V
DC Input Voltage............................................ –3.0V to +7.0V
Power Dissipation ..........................................................1.0W
Output Current, into Outputs (LOW) ............................ 20 mA
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ..................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Military
[1]
Ambient
Temperature
0
°
C to +70
°
C
–40
°
C to +85
°
C
–55
°
C to +125
°
C
V
CC
5V
±
10%
5V
±
10%
5V
±
10%
Electrical Characteristics
Over the Operating Range
[2]
7C470–15
7C472–15
7C474–15
Parame-
ter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
I
SB2
I
OS[3]
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Operating Current
Standby Current
Power-Down Current
Output Short Circuit Current
GND
≤
V
I
≤
V
CC
R
≥
V
IH
, GND
≤
V
O
≤
V
CC
V
CC
= Max.,
I
OUT
= 0 mA
All Inputs =
V
IH
Min.
All Inputs =
V
CC
–0.2V
Com’l
Mil/Ind
Com’l
Mil/Ind
Com’l
Mil/Ind
–90
20
25
–90
25
30
–10
–10
Description
Output HIGH Voltage
Output LOW Voltage
Test Conditions
V
CC
= Min., I
OH
= –2.0 mA
V
CC
= Min., I
OL
= 8.0 mA
Com’l
Mil/Ind
0.8
+10
+10
105
110
–10
–10
2.2
2.2
0.8
+10
+10
–10
–10
Min.
2.4
0.4
Max.
7C470–20
7C472–20
7C474–20
Min.
2.4
0.4
2.2
2.2
0.8
+10
+10
90
95
25
30
20
25
–90
mA
mA
mA
V
µA
µA
mA
Max.
7C470–25
7C472–25
7C474–25
Min.
2.4
0.4
Max.
Unit
V
V
V
V
CC
= Max., V
OUT
= GND
Notes:
1. T
A
is the “instant on” case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second.
2
CY7C470
CY7C472
CY7C474
Electrical Characteristics
Over the Operating Range
[2]
(continued)
7C470–40
7C472–40
7C474–40
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
I
SB2
I
OS[3]
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Operating Current
Standby Current
Power-Down Current
Output Short Circuit Current
GND
≤
V
I
≤
V
CC
R
≥
V
IH
, GND
≤
V
O
≤
V
CC
V
CC
= Max., I
OUT
= 0 mA
All Inputs = V
IH
Min.
All Inputs = V
CC
–0.2V
V
CC
= Max., V
OUT
= GND
Com’l
Mil/Ind
Com’l
Mil/Ind
Com’l
Mil/Ind
–10
–10
Test Conditions
V
CC
= Min., I
OH
= –2.0 mA
V
CC
= Min., I
OL
= 8.0 mA
Com’l
Mil/Ind
2.2
2.2
0.8
+10
+10
70
75
25
30
20
25
–90
mA
mA
mA
V
µA
µA
mA
Min.
2.4
0.4
Max.
Unit
V
V
V
Capacitance
[4]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 4.5V
Max.
10
12
Unit
pF
pF
AC Test Loads and Waveforms
5V
OUTPUT
30 pF
INCLUDING
JIGAND
SCOPE
Equivalent to:
R2
333Ω
7C470–4
R1 500Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
R1 500Ω
3.0V
R2
333Ω
7C470–5
ALL INPUT PULSES
10%
90%
90%
10%
≤
5 ns
7C470–6
GND
≤
5 ns
(a)
(b)
THÉVENIN EQUIVALENT
200Ω
OUTPUT
2V
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
3
CY7C470
CY7C472
CY7C474
Switching Characteristics
Over the Operating Range
[5, 6]
7C470–15
7C472–15
7C474–15
Parameter
t
CY
t
A
t
RV
t
PW
t
LZR
t
DV[7]
t
HZ[7]
t
HWZ
t
SD
t
HD
t
EFD
t
EFL
t
HFD
t
AFED
t
RAE
t
WAF
Description
Cycle Time
Access Time
Recovery Time
Pulse Width
Read LOW to Low Z
Valid Data from Read HIGH
Read HIGH to High Z
Write HIGH to Low Z
Data Set-Up Time
Data Hold Time
E/F Delay
MR to E/F LOW
HF Delay
PAFE Delay
Effective Read from
Write HIGH
Effective Write from
Read HIGH
15
15
5
11
0
15
25
25
25
20
20
15
15
3
3
15
5
12
0
20
30
30
30
25
25
Min.
30
15
10
20
3
3
15
5
15
0
25
35
35
35
40
40
Max.
7C470–20
7C472–20
7C474–20
Min.
30
20
10
25
3
3
18
5
20
0
40
50
50
50
Max.
7C470–25
7C472–25
7C474–25
Min.
35
25
10
40
3
3
25
Max.
7C470–40
7C472–40
7C474–40
Min.
50
40
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
5. Test conditions assume signal transmission time of 5 ns or less, timing reference levels of 1.5V and output loading of the specified I
OL
/I
OH
and 30-pF load
capacitance, as in part (a) of AC Test Load and Waveforms, unless otherwise specified.
6. See the last page of this specification for Group A subgroup testing information.
7. t
HZR
and t
DVR
use capacitance loading as in part (b) of AC Test Loads. t
HZR
transition is measured at +500 mV from V
OL
and –500 mV from V
OH
. t
DVR
transition is measured
at the 1.5V level. t
HWZ
and t
LZR
transition is measured at
±100
mV from the steady state.
4
CY7C470
CY7C472
CY7C474
Switching Waveforms
Asynchronous Read and Write
t
CY
t
PW
t
RV
t
A
t
A
R
t
LZR
Q
0
–Q
8
t
PW
W
t
DVR
DATA VALID
t
CY
t
RV
t
HZR
DATA VALID
t
PW
t
SD
D
0
–D
8
t
HD
t
SD
t
HD
7C470–7
DATA VALID
DATA VALID
MasterReset (No Write to Programmable Flag Register)
t
CY
MR
R, W
t
HFD
HF
E/F
t
EFL
PAFE
t
AFED
7C470–8
t
PW
t
RV
t
RV
Master Reset (Write to Programmable Flag Register)
[8,9]
t
CY
t
PW
MR
t
PW
W(R)
t
CY
D
0
–D
8
(Q
0
–Q
8
)
VALID
t
HD
t
RV
t
RV
t
CY
t
RV
t
RV
7C470–9
Notes:
8. Waveform labels in parentheses pertain to writing the programmable flag register from the output port (Q
0
– Q
8
).
9. Master Reset (MR) must be pulsed LOW once prior to programming.
5
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