DRAM MODULE
M53210224DE2/DJ2 with Fast Page Mode
2M x 32 DRAM SIMM using 1Mx16, 1K Refresh, 5V
GENERAL DESCRIPTION
The Samsung M53210224D is a 2Mx32bits
Dynamic RAM
high density memory module. The Samsung M53210224D
consists of four CMOS 1Mx16bits DRAMs in 42-pin SOJ
packages mounted on a 72-pin glass-epoxy substrate. A 0.1
or 0.22uF decoupling capacitor is mounted on the printed cir-
cuit board for each DRAM. The M53210224D is a Single In-
line Memory Module with edge connections and is intended
for mounting into 72 pin edge connector sockets.
M53210224DE2/DJ2
FEATURES
• Part Identification
- M53210224DE2-C(1024 cycles/16ms Ref, SOJ, Solder)
- M53210224DJ2-C(1024 cycles/16ms Ref, SOJ, Gold)
• Fast Page Mode Operation
• C A S -before-R A S refresh capability
• R A S -only refresh capability
• TTL compatible inputs and outputs
• Single +5V
±
10% power supply
PERFORMANCE RANGE
Speed
-50
-60
• JEDEC standard PDPin & pinout
• PCB : Height(750mil), double sided component
t
R A C
50ns
60ns
t
C A C
15ns
15ns
t
R C
90ns
110ns
PIN CONFIGURATIONS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Symbol
V
SS
DQ0
DQ16
DQ1
DQ17
DQ2
DQ18
DQ3
DQ19
Vcc
NC
A0
A1
A2
A3
A4
A5
A6
Res(A10)
DQ4
DQ20
DQ5
DQ21
DQ6
DQ22
DQ7
DQ23
A7
Res(A11)
Vcc
A8
A9
RAS1
RAS0
NC
NC
Pin
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Symbol
NC
NC
Vss
CAS0
CAS2
CAS3
CAS1
RAS0
RAS1
NC
W
NC
DQ8
DQ24
DQ9
DQ25
DQ10
DQ26
DQ11
DQ27
DQ12
DQ28
Vcc
DQ29
DQ13
DQ30
DQ14
DQ31
DQ15
NC
PD1
PD2
PD3
PD4
NC
Vss
PIN NAMES
Pin Name
A0 - A9
DQ0 - DQ31
W
RAS0 , RAS1
CAS0 - CAS3
PD1 -PD4
Vcc
Vss
NC
Res
Function
Address Inputs
Data In/Out
Read/Write Enable
Row Address Strobe
Column Address Strobe
Presence Detect
Power(+5V)
Ground
No Connection
Reserved Pin
PRESENCE DETECT PINS (Optional)
Pin
PD1
PD2
PD3
PD4
50NS
NC
NC
Vss
Vss
60NS
NC
NC
NC
NC
* Pin connection changing available
S A M S U N G E L E C T R O N I C S C O . , LTD.
reserves the right to
change products and specifications without notice.
-1-
R e v. 0.0 (Oct. 1999)
DRAM MODULE
FUNCTIONAL BLOCK DIAGRAM
M53210224DE2/DJ2
DQ0-DQ15
RAS0
RAS
U0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
D Q 11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
U2
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15 A0-A9
RAS
RAS1
CAS0
LCAS
LCAS
CAS0
CAS1
UCAS
UCAS
CAS1
OE
OE
A0-A9
W
W
DQ16-DQ31
RAS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
D Q 11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
U3
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15 A0-A9
RAS
U1
CAS2
LCAS
LCAS
CAS2
CAS3
UCAS
UCAS
CAS3
OE
OE
A0-A9
W
W
A0-A9
W
Vcc
.1 or .22uF Capacitor
for each DRAM
Vss
To all DRAMs
-2-
R e v. 0.0 (Oct. 1999)
DRAM MODULE
ABSOLUTE MAXIMUM RATINGS *
Item
Voltage on any pin relative to V
S S
Voltage on V
C C
supply relative to V
S S
Storage Temperature
Power Dissipation
Short Circuit Output Current
Symbol
V
IN
, V
O U T
V
CC
T
stg
P
d
I
O S
M53210224DE2/DJ2
Rating
-1 to +7.0
-1 to +7.0
-55 to +150
4
50
Unit
V
V
°
C
W
mA
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended
periods may affect device reliability.
R E C O M M E N D E D O P E R A T I N G C O N D I T I O N S
(Voltage referenced to V
SS
, T
A
= 0 to 70
°
C)
Item
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
*1 : V
C C
+2.0V/20ns, Pulse width is measured at V
C C
.
*2 : -2.0V/20ns, Pulse width is measured at V
S S
.
Symbol
V
CC
V
SS
V
IH
V
IL
Min
4.5
0
2.4
-1.0
*2
Typ
5.0
0
-
-
Max
5.5
0
V
C C
+ 1
*1
0.8
Unit
V
V
V
V
D C A N D O P E R A T I N G C H A R A C T E R I S T I C S
(Recommended operating conditions unless otherwise noted)
M53210224DE2/DJ2
Symbol
I
C C 1
I
C C 2
I
C C 3
I
C C 4
I
C C 5
I
C C 6
I
I(L)
I
O(L)
V
OH
V
OL
Speed
Min
-50
-60
Don
′
t care
-50
-60
-50
-60
Don
′
t care
-50
-60
Don
′
t care
Don
′
t care
-
-
Unit
Max
304
284
8
304
284
184
164
4
304
284
20
10
-
0.4
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
uA
uA
V
V
-
-
-
-
-
-
-
-
-20
-10
2.4
-
I
C C 1
: Operating Current * (R A S , L C A S or U C A S , Address cycling @
t
R C
=min)
I
C C 2
: Standby Current (R A S = L C A S = U C A S = W = V
IH
)
I
C C 3
: R A S Only Refresh Current * (L C A S = U C A S = V
IH
, R A S cycling @
t
R C
=min)
I
C C 4
: Fast Page Mode Current * (R A S =V
IL
, L C A S or U C A S cycling :
t
P C
=min)
I
C C 5
: Standby Current (R A S = L C A S = U C A S = W =Vcc-0.2V)
I
C C 6
: C A S -Before- R A S Refresh Current * (R A S and C A S cycling @
t
R C
=min)
I
I(L)
: Input Leakage Current (Any input 0
≤
V
IN
≤
Vcc+0.5V, all other pins not under test=0 V)
I
O(L)
: Output Leakage Current(Data Out is disabled, 0V
≤
V
O U T
≤
Vcc)
V
O H
: Output High Voltage Level (I
O H
= -5mA)
V
O L
: Output Low Voltage Level (I
O L
= 4.2mA)
* N O T E
: I
C C 1
, I
C C 3
, I
C C 4
and I
C C 6
are dependent on output loading and cycle rates. Specified values are obtained with the output open.
I
C C
is specified as an average current. In I
C C 1
and I
C C 3
, address can be changed maximum once while R A S = V
IL
. In I
C C 4
,
address can be changed maximum once within one page mode cycle,
t
P C
.
-3-
R e v. 0.0 (Oct. 1999)
DRAM MODULE
C A P A C I TA N C E
(T
A
= 25
°
C, V
C C
=5V, f = 1MHz)
Item
Input capacitance[A0-A9]
Input capacitance[W ]
Input capacitance[R A S 0 , R A S 1 ]
Input capacitance[C A S 0 - C A S 3 ]
Input/Output capacitance[DQ0-31]
Symbol
C
IN1
C
IN2
C
IN3
C
IN4
C
DQ
M in
-
-
-
-
-
M53210224DE2/DJ2
Max
35
45
40
30
30
Unit
pF
pF
pF
pF
pF
A C C H A R A C T E R I S T I C S
(0
°
C
≤
T
A
≤
70
°
C, V
C C
=5.0V
±
10%. See notes 1,2.)
Test condition : V
ih
/V
il
=2.4/0.8V, V
oh
/V
ol
=2.4/0.4V, Output loading CL=100pF
Parameter
Random read or write cycle time
Access time from R A S
Access time from C A S
Access time from column address
C A S to output in Low-Z
Output buffer turn-off delay
Transition time(rise and fall)
R A S precharge time
R A S pulse width
R A S hold time
C A S hold time
C A S pulse width
R A S to C A S delay time
R A S to column address delay time
C A S to R A S precharge time
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
Column address to R A S lead time
Read command set-up time
Read command hold referenced to C A S
Read command hold referenced to R A S
Write command hold time
Write command pulse width
Write command to R A S lead time
Write command to C A S lead time
Data-in set-up time
Data-in hold time
Refresh period
Write command set-up time
C A S setup time( C A S -before-R A S refresh)
C A S hold time(C A S -before-R A S refresh)
R A S precharge to C A S hold time
Access time from C A S precharge
Symbol
M in
-50
Max
Min
110
50
13
25
0
0
3
30
50
13
50
13
20
15
5
0
10
0
10
25
0
0
0
10
10
13
13
0
10
16
0
5
10
5
30
0
5
10
5
35
10K
37
25
10K
15
50
0
0
3
40
60
15
60
15
20
15
5
0
10
0
10
30
0
0
0
10
10
15
15
0
10
16
10K
45
30
10K
15
50
60
15
30
-60
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
3
7
9
9
8
8
4
10
3,4
3,4,5
3,10
3
6
2
Unit
Note
t
R C
t
R A C
t
C A C
t
A A
t
C L Z
t
O F F
t
T
t
R P
t
R A S
t
R S H
t
C S H
t
C A S
t
R C D
t
R A D
t
C R P
t
A S R
t
R A H
t
A S C
t
C A H
t
RAL
t
R C S
t
R C H
t
R R H
t
W C H
t
W P
t
R W L
t
C W L
t
D S
t
D H
t
R E F
t
W C S
t
C S R
t
C H R
t
R P C
t
CPA
90
-4-
R e v. 0.0 (Oct. 1999)
DRAM MODULE
A C C H A R A C T E R I S T I C S
(0
°
C
≤
T
A
≤
70
°
C, V
C C
=5.0V
±
10%. See notes 1,2.)
Test condition : V
ih
/V
il
=2.4/0.8V, V
oh
/V
ol
=2.4/0.4V, Output loading CL=100pF
Parameter
Fast page mode cycle time
C A S precharge time(Fast page cycle)
R A S pulse width(Fast page cycle)
W to R A S precharge time(C-B-R refresh)
W to R A S hold time(C-B-R refresh)
Symbol
Min
-50
Max
Min
40
10
200K
60
10
10
M53210224DE2/DJ2
-60
Max
Unit
ns
ns
200K
ns
ns
ns
Note
t
P C
t
C P
t
R A S P
t
W R P
t
W R H
35
10
50
10
10
NOTES
1. An initial pause of 200us is required after power-up followed
by any 8 R A S -only or C A S -before-R A S refresh cycles before
proper device operation is achieved.
2. V
IH
(min) and V
IL
(max) are reference levels for measuring
timing of input signals. Transition times are measured
between V
IH
(min) and V
IL
(max) and are assumed to be 5ns
for all inputs.
9. These parameter are referenced to the C A S leading edge in
3. Measured with a load equivalent to 2 TTL loads and 100pF.
4. Operation within the
t
R C D
(max) limit insures that
t
R A C
(max)
can be met.
t
R C D
(max) is specified as a reference point only.
If
t
R C D
is greater than the specified
t
R C D
(max) limit, then
access time is controlled exclusively by
t
C A C
.
5. Assumes that
t
R C D
≥
t
R C D
(max).
6. This parameter defines the time at which the output achieves
the open circuit condition and is not referenced to V
O H
or
V
OL
.
early write cycles.
10. Operation within the
t
R A D
(max) limit insures that
t
R A C
(max)
can be met.
t
R A D
(max) is specified as reference point only. If
8. Either
t
R C H
or
t
R R H
must be satisfied for a read cycle.
7.
t
W C S
is non-restrictive operating parameter. It is included in
the
data
sheet
as
electrical
characteristic s
only.
If
t
W C S
≥
t
W C S
(min), the cycle is an early write cycle and the
data out pin will remain high impedance for the duration of
the cycle.
t
R A D
is greater than the specified
t
R A D
(max) limit, then
access time is controlled by
t
A A
.
-5-
R e v. 0.0 (Oct. 1999)
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