*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model
AD7862AR-10
AD7862BR-10
AD7862ARS-10
AD7862AN-10
AD7862SQ-10
AD7862AR-3
AD7862BR-3
AD7862ARS-3
AD7862AN-3
AD7862AR-2
AD7862ARS-2
REV. 0
Input
Input
±
10 V
±
10 V
±
10 V
±
10 V
±
10 V
±
2.5 V
±
2.5 V
±
2.5 V
±
2.5 V
0 V to 2.5 V
0 V to 2.5 V
Relative
Accuracy
±
1 LSB
±
1 LSB
±
1 LSB
±
1 LSB
±
1 LSB
±
1 LSB
±
1 LSB
±
1 LSB
±
1 LSB
±
1 LSB
±
1 LSB
Temperature
Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–3–
Package
Description
28-Bit Small Outline Package
28-Bit Small Outline Package
28-Bit Shrink Small Outline Package
28-Bit Plastic DIP
28-Bit Cerdip
28-Bit Small Outline Package
28-Bit Small Outline Package
28-Bit Shrink Small Outline Package
28-Plastic DIP
28-Bit Small Outline Package
28-Bit Shrink Small Outline Package
Package
Option
R-28
R-28
RS-28
N-28
Q-28
R-28
R-28
RS-28
N-28
R-28
RS-28
AD7862
TIMING CHARACTERISTICS
Parameter
t
CONV
t
ACQ
Parallel Interface
t
1
t
2
t
3
t
4
t
5 3
t
6 4
t
7
A, B
Versions
3.6
0.3
0
0
35
35
12
60
5
30
40
1, 2
(V
DD
= +5 V
5%, AGND = DGND = 0 V, REF = Internal. All Specifications T
MIN
to T
MAX
unless
otherwise noted.)
S
Version
3.6
0.3
0
0
45
45
12
70
5
40
40
Units
µs
max
us max
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
Test Conditions/Comments
Conversion Time
Acquisition Time
CS
to
RD
Setup Time
CS
to
RD
Hold Time
CONVST
Pulse Width
Read Pulse Width
Data Access Time After Falling Edge of
RD
Bus Relinquish Time After Rising Edge of
RD
Time Between Consecutive Reads
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6 V.
2
See Figure 1.
3
Measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.0 V.
4
These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
Specifications subject to change without notice.
CONVST
t
3
BUSY
t
CONV
A0
CS
.........
t
1
t
2
t
4
t
5
t
6
V
A1
V
A2
V
B1
.........
t
7
RD
DATA
V
B2
Figure 1. Timing Diagram
1.6mA
TO
OUTPUT
PIN
50pF
200µA
+1.6V
Figure 2. Load Circuit for Access Time and Bus Relinquish Time
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7862 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
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