IS45S16160C-7TLA1 datasheet, PDF

Datasheet> All Categories > storage> storage> IS45S16160C-7TLA1

IS45S16160C-7TLA1: DescriptionSynchronous DRAM, 16MX16, 5.4ns, CMOS, PDSO54, 0.400 INCH, 0.8 MM PITCH, LEAD FREE, TSOP2-54; Categorystorage storage; File Size2MB，40 Pages; ManufacturerIntegrated Silicon Solution ( ISSI ); Environmental Compliance

Download Datasheet Parametric Compare View All

IS45S16160C-7TLA1 Overview

Synchronous DRAM, 16MX16, 5.4ns, CMOS, PDSO54, 0.400 INCH, 0.8 MM PITCH, LEAD FREE, TSOP2-54

IS45S16160C-7TLA1 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Integrated Silicon Solution ( ISSI )
Parts packaging code	TSOP2
package instruction	TSOP2, TSOP54,.46,32
Contacts	54
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	5.4 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	143 MHz
I/O type	COMMON
interleaved burst length	1,2,4,8
JESD-30 code	R-PDSO-G54
JESD-609 code	e3
length	22.22 mm
memory density	268435456 bit
Memory IC Type	SYNCHRONOUS DRAM
memory width	16
Humidity sensitivity level	3
Number of functions	1
Number of ports	1
Number of terminals	54
word count	16777216 words
character code	16000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	16MX16
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Encapsulate equivalent code	TSOP54,.46,32
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	1.2 mm
self refresh	YES
Continuous burst length	1,2,4,8,FP
Maximum standby current	0.005 A
Maximum slew rate	0.185 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	40
width	10.16 mm

IS45S16160C-7TLA1 Preview

IS45S83200C

IS45S16160C

256 Mb Single Data Rate Synchronous DRAM

APRIL 2009

IS45S83200C

is organized as 4-bank x 8,388,608-word x 8-bit Synchronous DRAM with LVTTL interface and

IS45S16160C

is organized as 4-bank x 4,194,304-word x 16-bit. All inputs and outputs are referenced to

the rising edge of

CLK.

IS45S83200C

and

IS45S16160C

achieve very high speed data rates up to 166MHz, and

are suitable for main

memories or graphic memories in computer systems.

General Description

- Single 3.3V ±0.3V power supply

- Max. Clock frequency :

- 6:166MHz<3-3-3>/-7:143MHz<3-3-3>/-75:133MHz<3-3-3>

- Fully synchronous operation referenced to clock rising edge

- 4-bank operation controlled by BA0,BA1(Bank Address)

- /CAS latency- 2/3 (programmable)

- Burst length- 1/2/4/8/FP (programmable)

- Burst type- Sequential and interleave burst (programmable)

- Byte Control-

LDQM

and

UDQM

(IS45S16160C)

- Random column access

- Auto precharge / All bank precharge controlled by A10

- Auto and self refresh

- 8192 refresh cycles /64ms

- LVTTL Interface

- Package

400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch

Pb-free package is available

Features

notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-

est version of this device speciﬁcation before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — www.issi.com

Rev.

04/02/09

IS45S83200C

IS45S16160C

CLK

CKE

/CS

/RAS

/CAS

/WE

DQ0-15

: Master Clock

: Clock Enable

: Chip Select

: Row Address Strobe

: Column Address Strobe

: Write Enable

: Data I/O

DQM

A0-12

BA0,1

Vdd

VddQ

VSS

VSSQ

: Output Disable / Write Mask

: Address Input

: Bank Address

: Power Supply

: Power Supply for Output

: Ground

: Ground for Output

Integrated Silicon Solution, Inc. — www.issi.com

Rev.

04/02/09

IS45S83200C

IS45S16160C

Note: This figure shows the IS45S83200C.

The IS45S16160C configuration is 8192x512x16 of cell array and DQ0-15

Integrated Silicon Solution, Inc. — www.issi.com

Rev.

04/02/09

IS45S83200C

IS45S16160C

Pin Descriptions

SYMBOL

TYPE

DESCRIPTION

Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive

edge of CLK. CLK also increments the internal burst counter and controls the output registers.

Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the

clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle),

ACTIVE POWER-DOWN (row active in any bank), DEEP POWER DOWN (all banks idle), or

CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the

device enters power-down and self refresh modes, where CKE becomes asynchronous until

after exiting the same mode. The input buffers, including CLK, are disabled during power-down

and self refresh modes, providing low standby power. CKE may be tied HIGH.

Chip Select: /CS enables (registered LOW) and disables (registered HIGH) the command

decoder. All commands are masked when /CS is registered HIGH. /CS provides for external

bank selection on systems with multiple banks. /CS is considered part of the command code.

Command Inputs: /CAS, /RAS, and /WE (along with /CS) define the command being entered.

Input/Output Mask: DQM is sampled HIGH and is an input mask signal for write accesses and an

output enable signal for read accesses. Input data is masked during a WRITE cycle. The output

buffers are placed in a High-Z state (two-clock latency) when during a READ cycle. LDQM

corresponds to DQ0–DQ7, UDQM corresponds to DQ8–DQ15. LDQM and UDQM are

considered same state when referenced as DQM.

Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE or

PRECHARGE command is being applied. These pins also select between the mode register and

the extended mode register.

A0-12 specify the Row / Column Address in conjunction with BA0,1. The Row Address is

specified by A0-12. The Column Address is specified by A0-9(x8) and A0-8(x16). A10 is also

used to indicate precharge option. When A10 is high at a read / write command, an auto

precharge is performed. When A10 is high at a precharge command, all banks are precharged.

CLK

Input

CKE

Input

/CS

/CAS,

/RAS,

/WE

LDQM,

UDQM (x16)

DQM (x8)

Input

BA0, BA1

Input

A0–A12

Input

DQ0-DQ15 (x16)

DQ0-DQ7 (x8)

I/O

–

Supply

Data Input/Output: Data bus.

Internally Not Connected: These could be left unconnected, but it is recommended they be

connected or V

DQ Power: Provide isolated power to DQs for improved noise immunity.

DQ Ground: Provide isolated ground to DQs for improved noise immunity.

Core Power Supply.

Ground.

Integrated Silicon Solution, Inc. — www.issi.com

Rev.

04/02/09

IS45S83200C

IS45S16160C

ABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to V

Voltage on V

supply relative to V

Storage temperature

Power dissipation

Short circuit current

Symbol

OUT

, V

DDQ

STG

Value

-0.5 ~ 4.6

-65 ~ +150

1.0

Unit

NOTES:

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS

Parameter

Supply voltage

Recommended operating conditions (Voltage referenced to V

= 0V, ––

–Automotive

grade:

= -40 to 85 C)

Symbol

Vdd

ddQ

Input logic high voltage

Input logic low voltage

Output logic high voltage

Output logic low voltage

Input leakage current

Output leakage current

Min

3.0

2.0

-0.3

2.4

-5

Typ

3.3

Max

3.6

DDQ

+ 0.3

Unit

Note

= -0.1mA

= 0.1mA

0.8

0.4

Note:

1. VIH(max) = VDDQ

+ 2V

AC for pulse width

3ns

acceptable.

2. VIL(min) = -2V AC for pulse width

3ns

acceptable.

3. Any input 0V VIN VDD + 0.3V, all other pins are not under test = 0V.

4. Dout is disabled , 0V VOUT VDD.

CAPACITANCE

Clock

( Vdd =3.3V,

= 25°

f = 1MHz …

Symbol

Cclk

Cin

ADD

OUT

Parameter

Min

2.5

4.0

Max

4.0

5.0

6.5

Unit

Note

/CAS,/RAS,/WE,/CS,CKE,L/UDQM

Address

DQ0~DQ15

Integrated Silicon Solution, Inc. — www.issi.com

Rev.

04/02/09

More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

IS45S16160C-7TLA1 Related Products

	IS45S16160C-7TLA1	IS45S16160C-75TLA1
Description	Synchronous DRAM, 16MX16, 5.4ns, CMOS, PDSO54, 0.400 INCH, 0.8 MM PITCH, LEAD FREE, TSOP2-54	Synchronous DRAM, 16MX16, 5.4ns, CMOS, PDSO54, 0.400 INCH, 0.8 MM PITCH, LEAD FREE, TSOP2-54
Is it lead-free?	Lead free	Lead free
Is it Rohs certified?	conform to	conform to
Maker	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )
Parts packaging code	TSOP2	TSOP2
package instruction	TSOP2, TSOP54,.46,32	TSOP2, TSOP54,.46,32
Contacts	54	54
Reach Compliance Code	compliant	compliant
ECCN code	EAR99	EAR99
access mode	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
Maximum access time	5.4 ns	5.4 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	143 MHz	133 MHz
I/O type	COMMON	COMMON
interleaved burst length	1,2,4,8	1,2,4,8
JESD-30 code	R-PDSO-G54	R-PDSO-G54
JESD-609 code	e3	e3
length	22.22 mm	22.22 mm
memory density	268435456 bit	268435456 bit
Memory IC Type	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM
memory width	16	16
Humidity sensitivity level	3	3
Number of functions	1	1
Number of ports	1	1
Number of terminals	54	54
word count	16777216 words	16777216 words
character code	16000000	16000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
organize	16MX16	16MX16
Output characteristics	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSOP2	TSOP2
Encapsulate equivalent code	TSOP54,.46,32	TSOP54,.46,32
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE
Peak Reflow Temperature (Celsius)	260	260
power supply	3.3 V	3.3 V
Certification status	Not Qualified	Not Qualified
refresh cycle	8192	8192
Maximum seat height	1.2 mm	1.2 mm
self refresh	YES	YES
Continuous burst length	1,2,4,8,FP	1,2,4,8,FP
Maximum standby current	0.005 A	0.005 A
Maximum slew rate	0.185 mA	0.175 mA
Maximum supply voltage (Vsup)	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal surface	Matte Tin (Sn)	Matte Tin (Sn)
Terminal form	GULL WING	GULL WING
Terminal pitch	0.8 mm	0.8 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	40	40
width	10.16 mm	10.16 mm

Recommended Resources

Photoelectric automatic alarm circuit

Single tone burst circuit for microphone

Temperature difference measurement circuit

Simple home walkie-talkie circuit diagram

555 automatic cycle seven-color light control circuit

Ringing detection circuit

The Painful Experience of DSP Connecting to Emulator: Do not plug or unplug while power is on Do not plug or unplug while power is on Do not plug or unplug while power is on I have to say it three times. Although it is fine after plugging and unplugging ...; Jacktang DSP and ARM Processors

Thinking about using msp430 to realize function generator: I recently encountered a problem. I used MSP430 to make a function generator. I required a 50-ohm load and used an amplifier to achieve an output of more than 12V. The amplitude and frequency of the D...; yyj8902 Microcontroller MCU

C2000 floating point calculation notes - differences between CPU and CLA and error handling techniques: The C2000 microprocessor with C28x+FPU architecture adds some registers and instructions to the original C28x fixed-point CPU to support IEEE single-precision floating-point operations. The floating-p...; fish001 DSP and ARM Processors

When Kicad moves a line individually, the line is actually disconnected when moving. How to solve this problem?: Hello everyone, I just started using Kicad. When drawing a PCB, I want to drag the lines, but the lines are disconnected (as shown below). Can the entire line be linked like AD?...; xindela PCB Design

【Power Supply Q&A】Summary Post: In the event [url=https://bbs.eeworld.com.cn/thread-572200-1-1.html], raise your power supply questions & technical answers, improve your power supply knowledge, and win gifts~~[/url] Netizens raised ...; okhxyyo Power technology

EEWORLD University ---- Theoretical basis of IoT terminal development: Theoretical basis of IoT terminal development : https://training.eeworld.com.cn/course/27334Theoretical basis for IoT terminal development...; 桂花蒸 MCU

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components