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NM24C16TLEN

Description
EEPROM, 16KX1, Serial, CMOS, PDIP8, PLASTIC, DIP-8
Categorystorage    storage   
File Size25KB,7 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Download Datasheet Parametric View All

NM24C16TLEN Overview

EEPROM, 16KX1, Serial, CMOS, PDIP8, PLASTIC, DIP-8

NM24C16TLEN Parametric

Parameter NameAttribute value
MakerFairchild
Parts packaging codeDIP
package instructionDIP,
Contacts8
Reach Compliance Codeunknown
ECCN codeEAR99
Maximum clock frequency (fCLK)0.1 MHz
JESD-30 codeR-PDIP-T8
length9.817 mm
memory density16384 bit
Memory IC TypeEEPROM
memory width1
Number of functions1
Number of terminals8
word count16384 words
character code16000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize16KX1
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialSERIAL
Certification statusNot Qualified
Maximum seat height5.08 mm
Serial bus typeI2C
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)2.7 V
Nominal supply voltage (Vsup)3.3 V
surface mountNO
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
width7.62 mm
Maximum write cycle time (tWC)15 ms
AN-957
Interfacing the NM24C16
Serial EEPROM to the
8031 Microcontroller
INTRODUCTION
This applications note describes an interface between the Fair-
child Semiconductor NM24C16 serial EEPROM and an 8031
microcontroller. The interface between the devices uses 2 of the
8031 general purpose I/O port lines. Software has been devel-
oped that demonstrates how the NM24C16 can be accessed
through the I/O port bits. The circuit and software has been bench
tested and is ready to be used in an end user application.
Fairchild
Application Note 957
8031 INTERFACE DESCRIPTION
The interface to the 8031 uses 2 general purpose port lines. One
of the lines is used to drive the SCL input of the NM24C16, and the
other is used as an I/O port connected to the SDA line. The 8031
has very weak pull-ups on the output ports that provide a high
state. When an 8031 port bit is sending a high, the bit can be driven
externally and used as an input.
Port 1 of the 8031 provides the 2 I/O bits for the interface. Figure
1shows how the NM24C16 is connected to the 8031. The port bits
that were chosen for this interface are not especially significant.
Any 2 available port bits could be used as long as 1 can be
configured an output and 1 as an I /O with the weak pull-up.
Changes in the interface software to implement different port
placements would only require a change in the SDA and SCL port
definition at the top of the program.
NM24C16 DESCRIPTION
The NM24C16 is a 16k serial EEPROM that has a 2k by 8-bit
architecture. The NM24C16 uses the industry standard I
2
C serial
protocol for data transfers.
The I
2
C protocol allows several devices to share the same two
wire clock and data bus. Devices that are compatible with the
protocol fall into the categories of being either a master or a slave.
A master device controls the transfer of data, and a slave device
responds to the commands issued by a master. The NM24CXX
family of devices always fall into the category of slave devices
since they can not initiate data transfers.
The I
2
C protocol uses a clock (SCL) and a bidirectional data line
(SDA). When the NM24C16 is transmitting data an open drain
transistor is used to control the state of the SDA line. The SDA I/
O pulls the line low for a zero state, or places the line in high
impedance for a one state. An external pull-up resistor ensures a
“high” condition exists when the SDA line is in a high impedance
state.
Data is transfered back and forth by using predefined bit se-
quences. All transfers are initiated with a START condition (SDA
going low with SCL high) and terminated with a STOP condition
(SDA going high with SCL high). If an unexpected STOP is ever
detected the NM24C16 will return to the standby mode. Because
transitions of SDA when SCL is high have been defined as STOP
and START conditions, the SDA line must change only when SCL
is low while transfers are being performed.
10k
P1.0
P1.1
SDA V
CC
SCL A0
A1
A2
V
SS
NM24C16
8031
FIGURE 1. NM24C16 to 8031 Connections
SOFTWARE DESCRIPTION
The software listing demonstrates a byte read and byte write
operation. The read and write operations are implemented in
separate subroutines. Parameters to be passed into the subrou-
tines are stored in the SRAM portion of the 8031. The passed
parameters include address (hi-order and low-order) and data
(single byte) information. The variables are sometimes modified
during subroutine operation so they must be initialized immedi-
ately prior to a subroutine call. Expansions of the byte read and
write routines to implement sequential read and page write should
be straightforward.
The software also implements acknowledge (ACK) polling to
indicate when a write operation has completed. While the NM24C16
is actually changing the state of the EEPROM bits all input pins are
ignored. Once a write cycle has concluded the NM24C16 will
return an acknowledge when a valid slave address is issued. The
ACK polling routine repeatedly sends a slave address and check
to see if the X24C16 returns an acknowledge. A STOP condition
is issued once an ACK is received to return the NM24C16 to the
standby mode. Using acknowledge polling can significantly re-
duce the effective Write Cycle Time because the actual time
required is typically much less than the maximum specified in the
data sheet.
DATA TRANSFERS
There are just two types of data transfers used on the NM24C16,
a page write operation, and a sequential read operation. Byte write
and byte read operations are simply truncated versions of a page
write or sequential read.
The page write allows up to 16 bytes in a single page to be altered
during a single write operation. It is important to note that all
addresses to be altered must reside in the same 16 byte page. A
byte write is the same as a page write with the data in a single
address being altered.
The sequential read operation will allow read operations starting
at a user defined address and then allow successive addresses to
be read as long as the user continues to indicate that the read
operation is to continue. The byte read is simply a sequential read
from only a single address.
© 1998 Fairchild Semiconductor Corporation
1
www.fairchildsemi.com
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