NM24C17TLZEN datasheet, PDF - EEWORLD Datasheet

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NM24C17TLZEN: DescriptionEEPROM, 16KX1, Serial, CMOS, PDIP8, PLASTIC, DIP-8; Categorystorage storage; File Size35KB，10 Pages; ManufacturerFairchild; Websitehttp://www.fairchildsemi.com/

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NM24C17TLZEN Overview

EEPROM, 16KX1, Serial, CMOS, PDIP8, PLASTIC, DIP-8

NM24C17TLZEN Parametric

Parameter Name	Attribute value
Maker	Fairchild
Parts packaging code	DIP
package instruction	DIP,
Contacts	8
Reach Compliance Code	unknown
ECCN code	EAR99
Maximum clock frequency (fCLK)	0.1 MHz
JESD-30 code	R-PDIP-T8
length	9.817 mm
memory density	16384 bit
Memory IC Type	EEPROM
memory width	1
Number of functions	1
Number of terminals	8
word count	16384 words
character code	16000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	16KX1
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Parallel/Serial	SERIAL
Certification status	Not Qualified
Maximum seat height	5.08 mm
Serial bus type	I2C
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	NO
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
width	7.62 mm
Maximum write cycle time (tWC)	15 ms

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AN-794

Using an EEPROM—

IIC

Interface

NM24C02/03/04/05/08/09/

16/17

INTRODUCTION

Fairchild Semiconductor’s NM24C EEPROMs are designed to

interface with Inter-Integrated Circuit (IIC) buses and hardware.

Fairchild’s electrically erasable programmable read only memo-

ries (EEPROMs) offer valuable security features (write protec-

tion), two write modes, three read modes and a wide variety of

memory sizes. Applications for the IIC bus and NM24C memories

are included in SANs (small-area networks), stereos, televisions,

automobiles and other scaled-down systems that don’t require

tremendous speeds but instead cost efficiency and design sim-

plicity.

Fairchild

Application Note 794

ration used by the IIC interface compared to that of the

MICROWIRE™ and SPI interface, reduced board space and pin

count allows the designer to have more creative flexibility while

reducing interconnecting cost.

OPERATING Fairchild SEMICONDUCTOR’S

NM24Cs

The NM24C E

PROMs require only six simple operating codes for

transmitting or receiving bits of information over the 2-wire IIC bus.

These fields are explained in greater detail below and briefly

described hereafter: a start bit, a 7-bit slave address, a read/write

bit which defines whether the slave is a transmitter or receiver, an

acknowledge bit, message bits divided into 8-bit segments and a

stop bit.

For efficient and faster serial communication between devices,

the NM24C Family features page write and sequential read.

The NM24C03/C05/C09/C16/C17 Family offers a security feature

in addition to standard features found in the NM24C02/C04/C08/

C16 Family. The security feature is beneficial in that it allows Read

Only Memory (ROM) to be implemented in the upper half of the

memory to prevent any future programming in that particular chip

section; the remaining memory that has not been write protected

can still be programmed. The security feature in the NM24C03/

C05/C09/C17 Family does not require immediate implementation

when the device is interfaced to the IIC bus, which gives the

designer the option to choose this feature at a later date. Table 1

displays the following parameters: memory content, write protect

and the maximum number of individual IIC E

PROMs allowed on

an IIC bus at one time if the total line capacitance is kept below 400

pF.

Code used to interface the NM24Cs with Fairchild Semiconductor’s

COP8™ Microcontroller Family is listed in a latter section of this

application note for further information to the reader.

IIC

BACKGROUND

The IIC bus configuration is an amalgam of microcontrollers and

peripheral controllers. By definition: a device that transmits sig-

nals onto the IIC bus is the “transmitter” and a device that receives

signals is the “receiver”; a device that controls signal transfers on

the line in addition to controlling the clock frequency is the “master”

and a device that is controlled by the master is the “slave”. The

master can transmit or receive signals to or from a slave, respec-

tively, or control signal transfers between two slaves, where one

is the transmitter and the other is the receiver. It is possible to

combine several masters, in addition to several slaves, onto an IIC

bus to form a multimaster system. If more than one master

simultaneously tries to control the line, an arbitration procedure

decides which master gets priority. The maximum number of

devices connected to the bus is dictated by the maximum allow-

able capacitance on the lines, 400 pF, and the protocol’s address-

ing limit of 16k; typical device capacitance is 10 pF. Up to eight

PROMs can be connected to an IIC bus, depending on the size

of the memory device implemented.

Simplicity of the IIC system is primarily due to the bidirectional 2-

wire design, a serial data line (SDA) and serial clock line (SKL),

and to the protocol format. Because of the efficient 2-wire configu-

TABLE 1.

Part No.

NM24C02

NM24C03

NM24C04

NM24C05

NM24C08

NM24C09

NM24C16

NM24C17

Number of

256x8 Page Blocks

Write Protect

Feature

Yes

Max.

Parts

www.fairchildsemi.com

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