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MT46HC32M16LFCX-54LIT:B

Description
DDR DRAM, 32MX16, 5.4ns, CMOS, PBGA90, 9 X 13 MM, GREEN, PLASTIC, VFBGA-90
Categorystorage    storage   
File Size3MB,98 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Environmental Compliance  
Download Datasheet Parametric View All

MT46HC32M16LFCX-54LIT:B Overview

DDR DRAM, 32MX16, 5.4ns, CMOS, PBGA90, 9 X 13 MM, GREEN, PLASTIC, VFBGA-90

MT46HC32M16LFCX-54LIT:B Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerMicron Technology
Parts packaging codeBGA
package instructionVFBGA,
Contacts90
Reach Compliance Codecompliant
ECCN codeEAR99
access modeFOUR BANK PAGE BURST
Maximum access time5.4 ns
Other featuresAUTO/SELF REFRESH
JESD-30 codeR-PBGA-B90
JESD-609 codee1
length13 mm
memory density536870912 bit
Memory IC TypeDDR DRAM
memory width16
Number of functions1
Number of ports1
Number of terminals90
word count33554432 words
character code32000000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize32MX16
Package body materialPLASTIC/EPOXY
encapsulated codeVFBGA
Package shapeRECTANGULAR
Package formGRID ARRAY, VERY THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum seat height1 mm
self refreshYES
Maximum supply voltage (Vsup)1.95 V
Minimum supply voltage (Vsup)1.7 V
Nominal supply voltage (Vsup)1.8 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Silver/Copper (Sn/Ag/Cu)
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature30
width10 mm
512Mb: x16, x32 Mobile LPDDR SDRAM
Features
Mobile Low-Power DDR SDRAM
MT46H32M16LF – 8 Meg x 16 x 4 Banks
MT46H16M32LF – 4 Meg x 32 x 4 Banks
Features
V
DD
/V
DDQ
= 1.70–1.95V
1.2V I/O option V
DDQ
= 1.14–1.30V
Bidirectional data strobe per byte of data (DQS)
Internal, pipelined double data rate (DDR)architec-
ture; two data accesses per clock cycle
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge
DQS edge-aligned with data for READs;center-
aligned with data for WRITEs
4 internal banks for concurrent operation
Data masks (DM) for masking write data—one mask
per byte
Programmable burst lengths (BL): 2, 4, 8, or 16
Concurrent auto precharge option is supported
Auto refresh and self refresh modes
1.8V LVCMOS-compatible inputs
On-chip temp sensor to control self refresh rate
Partial-array self refresh (PASR)
Deep power-down (DPD)
Status read register (SRR)
Selectable output drive strength (DS)
Clock stop capability
64ms refresh
Table 1: Key Timing Parameters (CL = 3)
Speed Grade
-5
-54
-6
-75
Clock Rate (MHz)
200
185
166
133
Access Time
5.0ns
5.0ns
5.0ns
6.0ns
Options
V
DD
/V
DDQ
1.8V/1.8V
1.8V/1.2V
1
Configuration
32 Meg x 16 (8 Meg x 16 x 4 banks)
16 Meg x 32 (4 Meg x 32 x 4 banks)
Row-size option
JEDEC-standard option
Reduced page-size option
1
Plastic green package
60-ball VFBGA (8mm x 9mm)
2
90-ball VFBGA (10mm x 13mm)
3
90-ball VFBGA (9mm x 13mm)
3
Timing – cycle time
5ns @ CL = 3
5.4ns @ CL = 3
6ns @ CL = 3
7.5ns @ CL = 3
Power
Standard I
DD2
/I
DD6
Low-power I
DD2
/I
DD61
Operating temperature range
Commercial (0˚ to +70˚C)
Industrial (–40˚C to +85˚C)
Design revision
Notes:
Marking
H
HC
32M16
16M32
LF
LG
BF
CM
CX
-5
-54
-6
-75
None
L
None
IT
:B
1. Contact factory for availability.
2. Only available for x16 configuration.
3. Only available for x32 configuration.
PDF: 09005aef82d5d305
512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2004 Micron Technology, Inc. All rights reserved.

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