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Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> 9248AG-192LF
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9248AG-192LF

Description
TSSOP-28, Tube
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size352KB，14 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
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9248AG-192LF Overview

TSSOP-28, Tube

9248AG-192LF Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeTSSOP
package instruction4.40 MM, 0.65 MM PITCH, GREEN, MO-153, TSSOP-28
Contacts28
Manufacturer packaging codePGG28
Reach Compliance Codeunknown
ECCN codeEAR99
JESD-30 codeR-PDSO-G28
JESD-609 codee3
length9.7 mm
Humidity sensitivity level1
Number of terminals28
Maximum operating temperature70 °C
Minimum operating temperature
Maximum output clock frequency66.6 MHz
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP28,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
power supply2.5,3.3 V
Master clock/crystal nominal frequency14.318 MHz
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum slew rate80 mA
Maximum supply voltage3.465 V
Minimum supply voltage3.135 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width4.4 mm
uPs/uCs/peripheral integrated circuit typeCLOCK GENERATOR, PROCESSOR SPECIFIC

9248AG-192LF Preview

ICS9248-192
Frequency Timing Generator for Transmeta Systems
Recommended Application:
Transmeta
Output Features:
• 1CPU(2.5V or 3.3V selectable) up to 66.6MHz &
overclocking of 66MHz.
•
•
•
•
6 PCI (3.3V) @ 33.3MHz (all are free running
selectable).
1 REF (3.3V) at 14.318MHz.
1 48MHz (3.3V).
1 24_48MHz selectable output.
Pin Configuration
GNDREF
X1
X2
PD#
PCICLK0
PCICLK1
PCICLK2
GNDPCI
VDDPCI
PCICLK3
PCICLK4
PCICLK5
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDDREF
REF
CPU_STOP#
VDDLCPU
GNDLCPU
CPUCLK0
PCI_STOP#
GND_Core
VDD_Core
SEL66/60#
VDD48
GND48
48MHz/CPU3.3v_2.5V#sel
24-48MHz/Sel48_24#
Features:
• Supports Spread Spectrum modulation for CPU and
PCI clocks, default -0.4 downspread.
• Efficient Power management scheme through stop
clocks and power down modes.
• Uses external 14.318MHz crystal, no external load
cap required for CL=18pF crystal.
• 28-pin TSSOP package, 4.40mm (173mil).
Skew Characteristics:
• CPU – CPU <175ps
• PCI – PCI < 500ps
• CPU(early) – PCI = 1.5ns – 4ns.
28-Pin TSSOP
Block Diagram
PLL2
/2
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
48MHz
24_48MHz
REF
CPU
DIVDER
Stop
CPUCLK0
SEL48_24#
CPU3.3V_2.5V#sel
SEL66/60#
PD#
PCI_STOP#
CPU_STOP#
SDATA
SCLK
Control
Logic
Config.
Reg.
PCI
DIVDER
Stop
6
PCICLK (5:0)
Power Groups
VDD_Core, GND_Core = PLL core
VDDREF, GNDREF = REF, X1, X2
VDDPCI, GNDPCI = PCICLK (5:0)
VDD48, GND48 = 48MHz (1:0)
0540F—10/27/05
ICS9248-192
ICS9248-192
Pin Descriptions
Pin number
1
2
3
4
12, 11, 10, 7, 6, 5
8
9
15
13
14
16
48MHz
17
18
GND48
VDD48
Output
Power
Power
Pin name
GNDREF
X1
X2
PD#
PCICLK (5:0)
GNDPCI
VDDPCI
Sel48_24#
24_48MHz
SDATA
SCLK
CPU3.3-2.5#
Type
Power
Input
Output
Input
Output
Power
Power
Input
Output
I/O
IN
Input
Description
Ground for 14.318 MHz reference clock outputs
14.318 MHz crystal input
14.318 MHz crystal output
Asynchronous active low input pin used to power down the device
into a low power state. The internal clocks are disabled and the
VCO and the crystal are stopped. The latency of the power down
will not be greater than 3ms.
3.3V PCI clock outputs, free running selectable
Ground for PCI clock outputs
3.3V power for the PCI clock outputs
Selects 24MHz (0) or 48MHz (1) output
Selectable output either 24MHz or 48MHz
Data pin for I
2
C circuitry 5V tolerant
Clock pin of I
2
C circuitry 5V tolerant
3.3 (1) or 2.5 (0) VDD buffer strength selection, has pullup to VDD,
nominal 30K resistor.
3.3V 48 MHz clock output, fixed frequency clock typically used with
USB devices
Ground for 48 MHz clocks
3.3V power for 48/24 MHz clocks
Control for the frequency of clocks at the
CPU & PCICLK output pins.
"0" = 60 MHz. "1" = 66.6 MHz.
The PCI clock is multiplexed to run at 33.3 MHz
for both selected cases.
Isolated 3.3V power for core
Isolated ground for core
Synchronous active low input used to stop the PCICLK in active low
state. It will not effect PCICLK_F or any other outputs.
CPU clock outputs selectable 2.5V or 3.3V.
Ground for CPU clock outputs
2.5V or 3.3V power for CPU clock outputs
Asynchronous active low input pin used to stop the CPUCLK in
active low state, all other clocks will continue to run. The CPUCLK
will have a "Turnon " latency of at least 3 CPU clocks.
3.3V 14.318 MHz reference clock output
3.3V power for 14.318 MHz reference clock outputs.
19
SEL 66/60#
Input
20
21
22
23
24
25
26
27
28
VDD_Core
GND_Core
PCI_Stop#
CPUCLK0
GNDLCPU
VDDLCPU
CPU_STOP#
REF
VDDREF
Power
Power
Input
Output
Power
Power
Input
Output
Power
0540F—10/27/05
2
ICS9248-192
CPU Select Functions
SEL 66/60#
0
1
CPU (MHz)
60MHz
66.6MHz
Power Management
Clock Enable Configuration
C P U _ S TO P #
X
0
0
1
1
P C I _ S TO P #
X
0
1
0
1
P W R _ DW N #
0
1
1
1
1
CPUCLK
L ow
Low
Low
60/66.6MHz
60/66.6MHz
PCICLK
L ow
Low
33.3 MHz
Low
33.3 MHz
REF
Stopped
Running
Running
Running
Running
Cr ystal
Off
Running
Running
Running
Running
VCOs
Off
Running
Running
Running
Running
Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During
power up and power down operations using the PD# pin will not cause clocks of a short or longer pulse than that of
the running clock. The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock
network charging circuitry. Board routing and signal loading may have a large impact on the initial clock distortion also.
ICS9248-192 Power Management Requirements
SIGNAL
CPU_ STOP#
PCI_STOP#
PD#
SIGNAL STATE
0 (Disabled)
2
1 (Enabled)
1
0 (Disabled)
2
1 (Enabled)
1
1 ( N o r m a l O p e ra t i o n )
3
0 (Power Down)
4
L a t e n cy
No. of rising edg es of free
running PCICLK
1
1
1
1
3ms
2max
Notes.
1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.
2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.
3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.
4. Power down has controlled clock counts applicable to CPUCLK, PCICLK only.
The REF will be stopped independant of these.
0540F—10/27/05
3
ICS9248-192
The information in this section assumes familiarity with I
2
C programming.
General I
2
C serial interface information
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends a dummy command code
ICS clock will
acknowledge
Controller (host) sends a dummy byte count
ICS clock will
acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 6
• ICS clock will
acknowledge
each byte
one at a time.
How to Write:
Controller (Host)
Start Bit
Address
D2
(H)
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Stop Bit
ICS (Slave/Receiver)
How to Read:
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the
byte count
Controller (host) acknowledges
ICS clock sends first byte
(Byte 0) through byte 6
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
•
•
•
•
•
•
•
•
How to Read:
Controller (Host)
Start Bit
Address
D3
(H)
ICS (Slave/Receiver)
ACK
ACK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Stop Bit
Notes:
1.
2.
3.
4.
5.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the
latches for verification.
Read-Back will support Intel PIIX4 "Block-Read" protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the
controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability
to stop after any complete byte has been transferred. The Command code and Byte count shown above
must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is
issued.
At power-on, all registers are set to a default condition, as shown.
6.
0540F—10/27/05
4
ICS9248-192
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Bit2
FS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
2,7:4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bit7
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
Bit6
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
Bit5
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
Bit4
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
CPU
60
60
60
60
66.6
66.6
66.6
66.6
67.32
68.64
69.96
72.6
61.5
63
64
65
60
66.6
50
48
58.8
57.6
56.4
54
60
60
60
60
66.6
PCI
30
30
30
30
33.3
33.3
33.3
33.3
33.66
34.32
34.98
36.3
30.75
31.5
32
32.5
30
33.3
25
24
29.4
28.8
28.2
27
30
30
30
30
33.3
Spread %
-0.4 % down spread
-0.6 % down spread
-0.8 % down spread
-1.0 % down spread
-0.4 % down spread
-0.6 % down spread
-0.8 % down spread
-1.0 % down spread
2% over-clocking
4% over-clocking
6% over-clocking
10% over-clocking
over-clocking
over-clocking
over-clocking
over-clocking
+/- 0.5% center spread
+/- 0.5% center spread
under-clocking
under-clocking
2% under-clock
4% under-clock
6% under-clock
10% under-clock
-1.4 % down spread
-1.6 % down spread
-1.8 % down spread
-2.0 % down spread
-1.4 % down spread
PWD
00000
Bit3
Bit1
Bit0
66.6
33.3
-1.6 % down spread
1
1
0
1
66.6
33.3
-1.8 % down spread
1
1
1
0
66.6
33.3
-2.0 % down spread
1
1
1
1
Hardware latch inputs can only access these frequencies
0-Frequency is seleced by hardware select. Latched input
1-Frequency is seleced by Bit 2, 7:4
0-Normal 1-Spread spectrun Enabled
0-Running 1-Tristate all outputs
0
0
0
Note:
PWD = Power-Up Default
0540F—10/27/05
5
More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

9248AG-192LF Related Products

9248AG-192LF 9248AG-192LFT
Description TSSOP-28, Tube TSSOP-28, Reel
Brand Name Integrated Device Technology Integrated Device Technology
Is it lead-free? Lead free Lead free
Is it Rohs certified? conform to conform to
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Parts packaging code TSSOP TSSOP
package instruction 4.40 MM, 0.65 MM PITCH, GREEN, MO-153, TSSOP-28 4.40 MM, 0.65 MM PITCH, GREEN, MO-153, TSSOP-28
Contacts 28 28
Manufacturer packaging code PGG28 PGG28
Reach Compliance Code unknown compliant
ECCN code EAR99 EAR99
JESD-30 code R-PDSO-G28 R-PDSO-G28
JESD-609 code e3 e3
length 9.7 mm 9.7 mm
Humidity sensitivity level 1 1
Number of terminals 28 28
Maximum operating temperature 70 °C 70 °C
Maximum output clock frequency 66.6 MHz 66.6 MHz
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP TSSOP
Encapsulate equivalent code TSSOP28,.25 TSSOP28,.25
Package shape RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius) 260 260
power supply 2.5,3.3 V 2.5,3.3 V
Master clock/crystal nominal frequency 14.318 MHz 14.318 MHz
Certification status Not Qualified Not Qualified
Maximum seat height 1.2 mm 1.2 mm
Maximum slew rate 80 mA 80 mA
Maximum supply voltage 3.465 V 3.465 V
Minimum supply voltage 3.135 V 3.135 V
Nominal supply voltage 3.3 V 3.3 V
surface mount YES YES
technology CMOS CMOS
Temperature level COMMERCIAL COMMERCIAL
Terminal surface Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed
Terminal form GULL WING GULL WING
Terminal pitch 0.65 mm 0.65 mm
Terminal location DUAL DUAL
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED
width 4.4 mm 4.4 mm
uPs/uCs/peripheral integrated circuit type CLOCK GENERATOR, PROCESSOR SPECIFIC CLOCK GENERATOR, PROCESSOR SPECIFIC

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