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Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> SLG505YC264CTTR
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SLG505YC264CTTR

Description
Processor Specific Clock Generator, 400MHz, CMOS, PDSO64, TSSOP-64
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size269KB，30 Pages
ManufacturerSilego
Environmental Compliance
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SLG505YC264CTTR Overview

Processor Specific Clock Generator, 400MHz, CMOS, PDSO64, TSSOP-64

SLG505YC264CTTR Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerSilego
package instructionTSSOP-64
Reach Compliance Codeunknown
JESD-30 codeR-PDSO-G64
length17 mm
Number of terminals64
Maximum operating temperature70 °C
Minimum operating temperature
Maximum output clock frequency400 MHz
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Master clock/crystal nominal frequency14.318 MHz
Maximum seat height1.2 mm
Maximum supply voltage3.465 V
Minimum supply voltage3.135 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width6.1 mm
uPs/uCs/peripheral integrated circuit typeCLOCK GENERATOR, PROCESSOR SPECIFIC

SLG505YC264CTTR Preview

SLG505YC264C
Clock Synthesizer for Intel
PCI-Express Gen2 Chipset
Features
•
•
•
•
SLG505YC264C is fully compliant to Intel CK505 clock
specification revision 1.0
SRC clocks compliant to PCI-Express Gen2 reference
clock requirement (except SRC_0 and SRC_1)
TME (Trusted Mode Enable) input to disable over-clocking
support
Two programmable single-ended outputs - 25MHz for LAN
PHY with Wake-on-LAN support and 24.576MHz for
1394A controller
3.3 and low voltage (0.8V) I/O Power Supply
64 pin TSSOP Package
Output Summary
•
•
•
•
•
•
•
•
2- differential CPU clock outputs @ 0.8V
1 - selectable differential CPU/SRC clock output @ 0.8V
1 - selectable differential DOT96/SRC clock output @ 0.8V
9 - differential Serial Reference Clock (SRC) clock outputs
@ 0.8V
1 - selectable differential SATA/SRC clock output @ 0.8V
1 - single-ended 48MHz clock output @ 3.3V
6 - single-ended 33MHz clock outputs @ 3.3V
1 - single-ended 14.318MHz clock output @ 3.3V
•
•
Table 1. Frequency Select Table (FS_C, FS_B, FS_A)
F
S
_
C
0
0
0
0
1
1
1
1
F
S
_
B
0
0
1
1
0
0
1
1
F
S
_
A
0
1
0
1
0
1
0
1
DOT_
96
(MHz)
96.0
96.0
96.0
96.0
96.0
96.0
96.0
Pin Configuration
PCI_0/CLKREQ_A#
USB
(MHz)
48.0
48.0
48.0
48.0
48.0
48.0
48.0
VDD_PCI
PCI_1/CLKREQ_B#
TME/PCI_2
*CFG_0/PCI_3
PCI_4/SRC_5_EN
PCIF_5/ITP_EN
VSS_PCI
VDD_48
USB/FS_A
VSS_48
1
2
3
4
5
6
7
8 1
9
10
11
12
64
63
62
61
60
59
58
57
56
55
54
53
SCL
SDA
REF/FS_C/TEST_SEL
VDD_REF
XTAL_IN
XTAL_OUT
VSS_REF
FS_B/TEST_MODE
CKPWRGD/PD#
VDD_CPU
CPU_0
CPU_0#
VSS_CPU
CPU_1_AMT
CPU_1_AMT#
VDD_CPU_I/O
I/O_Vout
SRC_8/CPU_ITP
SRC_8#/CPU_ITP#
VDD_SRC_I/O
SRC_7/CLKREQ_F#
SRC_7#/CLKREQ_E#
VSS_SRC
SRC_6
SRC_6#
VDD_SRC
PCI_STOP#/SRC_5
CPU_STOP#/SRC_5#
VDD_SRC_I/O
SRC_10#
SRC_10
SRC_11/CLKREQ_H#
CPU
(MHz)
266.6
133.3
200.0
166.6
333.3
100.0
400.0
SRC
(MHz)
100.0
100.0
100.0
100.0
100.0
100.0
100.0
PCI
(MHz)
33.3
33.3
33.3
33.3
33.3
33.3
33.3
REF
(MHz)
14.318
14.318
14.318
14.318
14.318
14.318
14.318
Reserved
Table 2. PROG_SE_1 and PROG_SE_2 Configuration
B
1
b
4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B
1
b
3
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
B
1
b
2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
B
1
b
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
24.576MHz
24.576MHz
98.304MHz
27MHz
25MHz
25MHz (Free-running)
25MHz (Free-running)
Reserved
PROG_SE_1
Pin 17
SRC_1
SRC_1
(LCD_CLK Stdby)
LCD_CLK (-0.5% SS)
LCD_CLK (-1.0% SS)
LCD_CLK (-1.5% SS)
LCD_CLK (-2.0% SS)
LCD_CLK (-2.5% SS)
PROG_SE_2
Pin 18
SRC_1#
SRC_1#
(LCD_CLK Stdby)
LCD_CLK# (-0.5% SS)
LCD_CLK# (-1.0% SS)
LCD_CLK# (-1.5% SS)
LCD_CLK# (-2.0% SS)
LCD_CLK# (-2.5% SS)
24.576MHz
98.304MHz
98.304MHz
27MHz
25MHz
24.576MHz
25MHz
VDD_I/O
SRC_0/DOT_96
SRC_0#/DOT_96#
VSS_I/O
VDD_PLL3
SRC_1/PROG_SE_1
SRC_1#/PROG_SE_2
VSS_PLL3
VDD_PLL3_I/O
SRC_2/SATA
SRC_2#/SATA#
VSS_SRC
SRC_3/CLKREQ_C#
SRC_3#/CLKREQ_D#
VDD_SRC_I/O
SRC_4
SRC_4#
VSS_SRC
SRC_9
SRC_9#
SRC_11#/CLKREQ_G#
SLG505YC264C
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Reserved
64-pin TSSOP
* contains internal pull-down
Other brands and names may be claimed as the property of others
Silego Technology, Inc.
000-0084505C-07
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Rev 0.7
Revised May 9, 2008
SLG505YC264C
Pin Description
Pin #
1
2
3
4
Name
PCI_0/CLKREQ_A#
VDD_PCI
PCI_1/CLKREQ_B#
TME/PCI_2
Type
I/O, SE
PWR
I/O, SE
I/O, SE
Description
Configurable PCI clock output or CLKREQ input.
3.3V power supply for outputs.
Configurable PCI clock output or CLKREQ input.
PCI clock output.
TME (Trusted Mode Enabled) strap input for PLL allocation and over-clocking
control. Please refer to Table 3. for detail descriptions.
PCI clock output.
PLL allocation control input. Please refer to Table 3. for detail descriptions. Con-
tains internal pull-down resistor.
PCI clock output.
When SRC_5_EN is sampled HIGH during CKPWRGD assertion, it will configure
PCI_STOP#/SRC_5 and CPU_STOP#/SRC_5# as SRC_5 and SRC_5# respec-
tively. When SRC_5_EN is sampled LOW, it will configure these pins as
PCI_STOP# and CPU_STOP#.
Free running PCI clock output.
When ITP_EN input is sampled HIGH during CKPWRGD assertion, it will config-
ure CPU_ITP/SRC_8 as CPU output.
Ground for outputs.
3.3V power supply for outputs.
USB clock output.
Frequency Select input to determine CPU output frequency.
Ground for outputs.
Low voltage I/O power supply for outputs.
Configurable SRC or 96 MHz DOT clock output.
Configurable SRC or 96 MHz DOT clock output.
Ground for outputs.
3.3V power supply for outputs.
Configurable SRC or Programmable SE output. SE output can be configured as
24.576MHz, 27MHz or 25MHz.
Configurable SRC or Programmable SE output. SE output can be configured as
24.576MHz, 27MHz or 25MHz.
Ground for outputs.
Low voltage I/O power supply for outputs.
Configurable Serial Reference clock for SATA or PCI Express device.
Configurable Serial Reference clock for SATA or PCI Express device.
Ground for outputs.
Configurable differential CPU clock output or CLKREQ input.
Configurable differential CPU clock output or CLKREQ input.
Low voltage I/O power supply for outputs.
Differential Serial Reference Clock output.
Page 2 of 30
5
CFG_0/PCI_3
O, SE
6
PCI_4/SRC_5_EN
I/O, SE
7
PCIF_5/ITP_EN
I/O, SE
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
VSS_PCI
VDD_48
USB/FS_A
VSS_48
VDD_I/O
SRC_0/DOT_96
SRC_0#/DOT_96#
VSS_I/O
VDD_PLL3
SRC_1/PROG_SE_
1
SRC_1#/PROG_SE
_2
VSS_PLL3
VDD_PLL3_I/O
SRC_2/SATA
SRC_2#/SATA#
VSS_SRC
SRC_3/CLKREQ_C
#
SRC_3#/CLKREQ_
D#
VDD_SRC_I/O
SRC_4
GND
PWR
I/O, SE
GND
PWR
O, DIF
O, DIF
GND
PWR
O, DIF/SE
O, DIF/SE
GND
PWR
O, DIF
O, DIF
GND
I/O
I/O
PWR
O, DIF
000-0084505C-07
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SLG505YC264C
Pin Description
(continued)
Pin #
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Name
SRC_4#
VSS_SRC
SRC_9
SRC_9#
SRC_11#/CLKREQ_
G#
SRC_11/CLKREQ_H
#
SRC_10
SRC_10#
VDD_SRC_I/O
CPU_STOP#/SRC_
5#
PCI_STOP#/SRC_5
VDD_SRC
SRC_6#
SRC_6
VSS_SRC
SRC_7#/CLKREQ_
E#
SRC_7/CLKREQ_F#
VDD_SRC_I/O
SRC_8#/CPU_ITP#
Type
O, DIF
GND
O, DIF
O, DIF
I/O
I/O
O, DIF
O, DIF
PWR
I/O
I/O
PWR
O, DIF
O, DIF
GND
I/O
I/O
PWR
O, DIF
Description
Differential Serial Reference Clock output.
Ground for outputs.
Differential Serial Reference Clock output.
Differential Serial Reference Clock output.
Configurable differential CPU clock output or CLKREQ input.
Configurable differential CPU clock output or CLKREQ input.
Differential Serial Reference Clock output.
Differential Serial Reference Clock output.
Low voltage I/O power supply for outputs.
Configurable CPU_STOP# input or differential Serial Reference Clock output.
Configurable PCI_STOP# input or differential Serial Reference Clock output.
3.3V power supply for outputs.
Differential Serial Reference Clock output.
Differential Serial Reference Clock output.
Ground for outputs.
Configurable differential CPU clock output or CLKREQ input.
Configurable differential CPU clock output or CLKREQ input.
Low voltage I/O power supply for outputs.
Selectable differential CPU or SRC output. It will configure as CPU clock when
ITP_EN is sampled HIGH. It will configure as SRC clock when ITP_EN is sam-
pled LOW.
Selectable differential CPU or SRC output. It will configure as CPU clock when
ITP_EN is sampled HIGH. It will configure as SRC clock when ITP_EN is sam-
pled LOW.
I/O voltage reference output.
Low voltage I/O power supply for outputs.
Differential CPU Clock output.
Differential CPU Clock output.
Ground for outputs.
Differential CPU Clock output.
Differential CPU Clock output.
3.3V power supply for outputs.
CKPWRGD is a 3.3V LVTTL iput. It acts as a level sensitive strobe to latch the
FS pins and other multiplexed inputs. After CKPWRGD assertion, it becomes a
real time input for asserting power down (active high).
47
SRC_8/CPU_ITP
O, DIF
48
49
50
51
52
53
54
55
56
I/O_Vout
VDD_CPU_I/O
CPU_1_AMT#
CPU_1_AMT
VSS_CPU
CPU_0#
CPU_0
VDD_CPU
CKPWRGD/PD#
O, SE
PWR
O, DIF
O, DIF
GND
O, DIF
O, DIF
PWR
I
000-0084505C-07
Page 3 of 30
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SLG505YC264C
Pin Description
(continued)
Pin #
57
Name
FS_B/TEST_MODE
Type
I
Description
Frequency Select input to determine CPU output frequency.
When in test mode, FS_B/TEST_MODE will configure outputs to run at REF or
Hi-Z. 0 = Hi-Z, 1 = REF
Ground for outputs.
14.318MHz crystal output.
14.318MHz crystal input.
3.3V power supply for outputs.
14.318 reference clock output.
When FS_C/TEST_SEL input is pulled to 3.3V during CKPWRGD# assertion,
the device will configure into TEST MODE. Refer to DC Parameters section for
FS input voltage threshold. After CKPWRGD assertion, this pin will be configured
as REF output.
Serial Interface bus data input and output.
Serial Interface bus clock input.
58
59
60
61
62
VSS_REF
XTAL_OUT
XTAL_IN
VDD_REF
REF/FS_C/TEST_S
EL
GND
O, SE
I
PWR
I/O, SE
63
64
SDA
SCL
I/O, SE
I
000-0084505C-07
Page 4 of 30
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SLG505YC264C
Block Diagram
XTAL_IN
XTAL
XTAL_OUT
CPU_0,
CPU_1_AMT
PLL1
CPU_ITP,
SRC_8
SRC_1, 3:7,
SRC_9:11
REF
SCL, SDA
PD#
CPU_STOP#
PCI_STOP#
CKPWRGD
PLL3
PCI_0:4,
PCIF_5
PROG_SE_0:1
(LCDCLK, 25MHz,
24.576MHz,
98.304MHz)
FS_A:C
ITP_EN
TME
CFG_0
TEST_MODE,
TEST_SEL
CLKREQ_A:H#
Serial Interface
&
Control Logic
PLL4
SATA / SRC_2
DOT_96 / SRC_0
PLL2
USB
Figure 1. Simplified Block Diagram
PLL Allocation & Over-clocking Control
Table 3. PLL configuration & over-clocking control (PCI_3/CFG_0 & PCI_2/TME HW strap inputs)
PCI_3/
CFG_0
Low
Low
Mid
Mid
High
High
PCI_2
/TME
Low
High
Low
High
Low
High
PLL
Allocation
Mode
0
0
1
1
2
3
PLL1
Outputs
CPU/SRC
/PCI
CPU/SRC
/PCI
CPU
CPU
CPU
CPU
SSC
Down
Down
Down
Down
Center
Center
PLL2
Outputs
USB
USB
USB
USB
USB
USB/
LAN25
SSC
N/A
N/A
N/A
N/A
N/A
N/A
PLL3
Outputs
LCDCLK
LCDCLK
SRC/PCI
SRC/PCI
SRC/PCI
SRC/PCI
SSC
Down
Down
Down
Down
Down
Down
PLL4
Outputs
OFF
OFF
OFF
OFF
OFF
24.576M
SSC
N/A
N/A
N/A
N/A
N/A
OFF
Over-
clocking
Support
Yes
No
Yes
No
Yes
Yes
000-0084505C-07
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