HMXNV0100
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HXNV0100
64K x 16 Non-Volatile
Magnetic RAM
The 64K x 16 radiation hardened low power nonvolatile
Magnetic RAM (MRAM) is a high performance 65,536
word x 16-bit magnetic random access memory with
industry-standard functionality.
The MRAM is designed for very high reliability.
Redundant write control lines, error correction coding
and low-voltage write protection ensure the correct
operation of the memory and that it is protected from
inadvertent writes.
Advanced Information
Integrated Power Up and Power Down circuitry controls
the condition of the device during power transitions.
It is fabricated with Honeywell’s radiation hardened
Silicon On Insulator (SOI) technology, and is designed
for use in low-voltage systems operating in radiation
environments. The MRAM operates over the full military
temperature range and is operated with 3.3
±
0.3V and
1.8
±
0.15 V power supplies.
FEATURES
Fabricated on S150 Silicon On
Insulator (SOI) CMOS
Underlayer Technology
150 nm Process (Leff = 130 nm)
Total Dose Hardness
≥
3x10
5
rad (SiO
2
)
Dose Rate Upset Hardness
≥
1x10
10
rad(Si)/s
Dose Rate Survivability
≥1x10
12
rad(Si)/s
Soft Error Rate
≤1x10
-10
upsets/bit-day
Neutron Hardness
≥
1x10
13
cm
-2
No Latchup
Read Cycle Time
≤
60 ns
Write Cycle Time
≤100ns
Typical Operating Power
≤500
mW
Unlimited Read/Write (>1E15
Cycles)
>10 years Power-Off Data
Retention
Synchronous Operation
Single-Bit Error Detection &
Correction (ECC)
Dual Power Supplies
•
•
1.8 V
±
0.15V, 3.3 V
±
0.3V
3.3V CMOS Compatible I/O
Operating Range is -55°C to
+125°C
Package: 64 Lead Shielded
ceramic Quad Flat Pack
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HMXNV0100
FUNCTIONAL BLOCK DIAGRAM
Bit Line Current Drivers
A(7:15)
CS
D
C
Q
Memory Array
65,536 x 16
ECC Array
65,536 x 5
WE
WE_AS
OE
D
C
Q
ECC Logic
NWI
Digit Line Current
Drivers
ECC_DISABLE
ERROR
A(0:6)
D
C
Q
Column Decoder
Data Input/Output
Read Circuits
DQ(0:15)
SIGNAL DESCRIPTION
Signal
A(0:6)
A–(7:15)
DQ(0:15)
CS
WE
WE_AS
OE
NWI_0
NWI_1
ECC_Disable
ERROR
Test_1
Test_2
VDD1
VDD2
Definition
Column Select Address Input. Signals which select a column within the
memory array.
Row Select Address Input. Signals which select a row within the
memory array.
Data Input/Output Signals. Bi-directional data pins which serve as data
outputs during a read operation and as data inputs during a write
operation.
Chip select. The rising edge of CS will clock in the address and WE
signals
Write Enable. This signal is latched to enable a write.
Write Enable Asynchronous – This signal can be used to delay the
beginning of the write cycle
Output Enable.
Not Write Inhibit – When set low, these signals inhibit writes to the
memory. A high level allows the memory to be written.
NWI(0) controls address locations A(15:0) = 0x0000 to 0x7FFF.
NWI(1) controls address locations A(15:0) = 0x1000 to 0xFFFF.
Error Correction Disable – Disables the error correction function.
ECC Error flag
These signals are for Honeywell test purposes only. These should be
grounded in normal operation.
DC Power Source Input: 1.8V
DC Power Source Input: 3.3V
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HMXNV0100
TRUTH TABLE
NWI
WE & WE_ASY
L
X
H
L
H
L
H
H
X: V
I
= V
IH
or V
IL
OE
L
L
H
X
MODE
Deselected
Disabled
Read
Write
DQ
High Z
High Z
Data Out
Data In
PACKAGE PINOUT
VDD1
GND
DQ(1)
DQ(0)
CS
NWI(0)
VDD2
VDD1
GND
NWI(1)
ECCDISABLE
ERROR
DQ(8)
DQ(9)
VDD2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GND
DQ(2)
DQ(3)
DQ(4)
DQ(5)
DQ(6)
DQ(7)
VDD2
GND
ADDR(0)
ADDR(1)
ADDR(2)
ADDR(3)
ADDR(4)
ADDR(5)
VDD1
HMXNV1000
GND
VDD2
ADR(6)
ADR(15)
WE
WE_ASY
OE
VDD2
VDD1
GND
ADDR(14)
ADDR(13)
ADDR(12)
ADDR(11)
GND
VDD1
RAM and ROM Functional Capability
This MRAM incorporates two write control
signals allowing the two sections of the
memory to be controlled independently.
The two NOT WRITE INHIBIT signals,
NWI(0) and NWI(1), allow one section of the
devices to operate as a RAM and the other
to operate as a ROM at the full control of the
user.
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VDD1
DQ(10)
DQ(11)
DQ(12)
DQ(13)
DQ(14)
DQ(15)
GND
VDD2
ADDR(7)
ADDR(8)
ADDR(9)
ADDR(10)
TEST
TEST
GND
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
HMXNV0100
SOI AND MAGNETIC MEMORY TECHNOLOGY
Honeywell’s S150 Silicon On Insulator
(SOI) is radiation hardened through the use
of advanced and proprietary design, layout
and process hardening techniques. The 150
nm process is a technology with a 32Å gate
oxide for 1.8 V transistors and 70Å gate
oxide for 3.3 V transistors. The memory
element is a magnetic tunnel junction (MTJ)
that is composed of a magnetic storage
layer structure and a magnetic pinned layer
structure separated by an insulating tunnel
barrier interlayer. During a write cycle, the
storage layer is written by the application of
two orthogonal currents of the desired
polarity using row-and-column addressing.
The resistance of the MTJ depends on the
magnetic state of the storage layer, which
uses the pinned layer structure as a
reference, and which enables sensing,
signal amplification, and readback. The
resistance change is a consequence of the
change in tunneling magnetoresistance
(TMR) between the storage and pinned
layers that depends on the magnetic state of
the storage layer. With read and write cycles
in excess of 10
15
, there is no wear-out.
ERROR CORRECTION CODE (ECC)
Hamming 5-Bit ECC
A 5-bit Hamming ECC is generated for all
data written into memory. This code allows
for the correction of all single-bit errors per
address. On a read cycle, the data is read
from memory and corrected, if necessary,
before being placed on the output data bus.
There is no change made to the actual data
in the memory cells based on the ECC
results. Actual data in memory is changed
only upon writing new values.
RADIATION CHARACTERISTIC
Transient Pulse Ionizing Radiation
Total Ionizing Radiation Dose
The MRAM will meet all stated functional
and electrical specifications over the entire
operating temperature range after the
specified total ionizing radiation dose. All
electrical and timing performance
parameters will remain within specifications
after rebound at typical VDD and T =125°C
extrapolated to ten years of operation. Total
dose hardness is assured by wafer level
testing of process monitor transistors and
RAM product using 10 KeV X-ray and Co60
radiation sources. Transistor gate threshold
shift correlations have been made between
10 KeV X-rays applied at a dose rate of
1x10
5
rad(SiO
2
)/min at T = 25°C and gamma
rays (Cobalt 60 source) to ensure that wafer
level X-ray testing is consistent with
standard military radiation test
environments.
The MRAM is capable of writing, reading,
and retaining stored data during and after
exposure to a transient ionizing radiation
pulse, up to the specified transient dose rate
upset specification, when applied under
recommended operating conditions. To
ensure validity of all specified performance
parameters before, during, and after
radiation (timing degradation during
transient pulse radiation is
±10%),
it is
suggested that stiffening capacitance be
placed near the package VDD
2
and ground
(GND).
It is recommended that the inductance
between the MRAM package leads and the
stiffening capacitance be less that 1.0 nH. If
there are no operate through or valid stored-
data requirements, typical circuit board
mounted de-coupling capacitors are
recommended. The MRAM will meet any
functional or electrical specification after
exposure to a radiation pulse up to the
transient dose rate survivability
specification, when applied under
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HMXNV0100
recommended operating conditions. Note
that the current conducted during the pulse
by the RAM inputs, outputs, and power
supply may significantly exceed the normal
operating levels. The application design
must accommodate these effects.
Neutron Radiation
The MRAM will meet any functional or timing
specification after exposure to the specified
neutron fluence under recommended
operating or storage conditions. This
assumes equivalent neutron energy of 1
MeV.
Soft Error Rate
The MRAM is capable of meeting the
specified Soft Error Rate (SER) under
recommended operating conditions. This
hardness level is defined by the Adams 90%
worst case cosmic ray environment for
geosynchronous orbits.
Latchup
The MRAM will not latch up under any of the
above radiation exposure conditions when
applied under recommended operating
conditions. Fabrication with the SIMOX
substrate material provides oxide isolation
between adjacent PMOS and NMOS
transistors and eliminates any potential
SCR-type latchup structures. Sufficient
transistor body tie connections to the p-
channel and n-channel substrates are made
to ensure no source/drain snapback occurs.
Radiation-Hardness Ratings
Parameter
Total Dose:
R-Level
F-Level
H-Level
Soft Error Rate:
Transient Dose
Rate Upset
Transient Dose
Rate Survivability
Neutron Fluence
Limits
≥
1 x 105
≥
3 x 105
≥
1 x 106
≤
1 x 10-10
≥
1 x 1010
≥
1 x 1012
1x10
13
Units
Rads(SiO
2
)
Test Conditions
VDD1= 1.95 Volts, VDD2= 3.6 Volts
TA = 25C, X-Ray or Co60
VDD1= 1.8 Volts, VDD2= 3.3 Volts
TC = -55 to 125°C
VDD1= 1.65 Volts, VDD2= 3.0 Volts
TC = 125°C Pulse Width = 1µsec, X-
Ray
VDD1= 1.95 Volts, VDD2= 3.6 Volts
TA = 25°C
Pulse Width = 50 nsec, X-Ray
1MeV equivalent energy
Upsets/bit-day
Rads(Si)/s
Rads(Si)/s
N/cm
-2
MAGNETIC FIELD CHARACTERISTICS
The MRAM will meet all stated functional
and electrical specifications over the entire
operating temperature range when exposed
to the specified magnetic fields. The
magnetic field hardening is achieved
through a combination of SOI technology
characteristics, circuit design and
specialized packaging.
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