MT55L128L36FT-12 datasheet, PDF

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MT55L128L36FT-12: DescriptionZBT SRAM, 128KX36, 9ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100; Categorystorage storage; File Size302KB，18 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/

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MT55L128L36FT-12 Overview

ZBT SRAM, 128KX36, 9ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100

MT55L128L36FT-12 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Micron Technology
Parts packaging code	QFP
package instruction	PLASTIC, MS-026BHA, TQFP-100
Contacts	100
Reach Compliance Code	not_compliant
ECCN code	3A991.B.2.A
Maximum access time	9 ns
Maximum clock frequency (fCLK)	83 MHz
I/O type	COMMON
JESD-30 code	R-PQFP-G100
JESD-609 code	e0
length	20 mm
memory density	4718592 bit
Memory IC Type	ZBT SRAM
memory width	36
Number of functions	1
Number of ports	1
Number of terminals	100
word count	131072 words
character code	128000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128KX36
Output characteristics	3-STATE
Exportable	YES
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Encapsulate equivalent code	QFP100,.63X.87
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	235
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum standby current	0.01 A
Minimum standby current	3.14 V
Maximum slew rate	0.25 mA
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	14 mm

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ADVANCE

4Mb: 256K x 18, 128K x 32/36

FLOW-THROUGH ZBT SRAM

4Mb

ZBT SRAM

FEATURES

•

High frequency and 100 percent bus utilization

Fast cycle times: 10ns, 11ns and 12ns

Single +3.3V

±5%

power supply (V

)

Separate +3.3V or +2.5V isolated output buffer supply

Advanced control logic for minimum control signal

interface

Individual BYTE WRITE controls may be tied LOW

Single R/W# (read/write) control pin

CKE# pin to enable clock and suspend operations

Three chip enables for simple depth expansion

Clock-controlled and registered addresses, data I/Os

and control signals

Internally self-timed, fully coherent WRITE

Internally self-timed, registered outputs to eliminate

the need to control OE#

SNOOZE MODE for reduced-power standby

Common data inputs and data outputs

Linear or Interleaved Burst Modes

Burst feature (optional)

Pin/function compatibility with 2Mb, 8Mb and 16Mb

ZBT SRAM

Automatic power-down

MT55L256L18F, MT55L128L32F,

MT55L128L36F; MT55L256V18F,

MT55L128V32F, MT55L128V36F

3.3V V

, 3.3V or 2.5V I/O

100-Pin TQFP*

(D-1)

*JEDEC-standard MS-026 BHA (LQFP).

GENERAL DESCRIPTION

The Micron

Zero Bus Turnaround

™

(ZBT

) SRAM family

employs high-speed, low-power CMOS designs using an

advanced CMOS process.

Micron’s 4Mb ZBT SRAMs integrate a 256K x 18,

128K x 32, or 128K x 36 SRAM core with advanced

synchronous peripheral circuitry and a 2-bit burst counter.

These SRAMs are optimized for 100 percent bus utilization,

eliminating any turnaround cycles for READ to WRITE, or

WRITE to READ, transitions. All synchronous inputs pass

through registers controlled by a positive-edge-triggered

single clock input (CLK). The synchronous inputs include

all addresses, all data inputs, chip enable (CE#), two

additional chip enables for easy depth expansion (CE2,

CE2#), cycle start input (ADV/LD#), synchronous clock

enable (CKE#), byte write enables (BWa#, BWb#, BWc#

and BWd#) and read/write (R/W#).

Asynchronous inputs include the output enable (OE#,

which may be tied LOW for control signal minimization),

clock (CLK) and snooze enable (ZZ, which may be tied

LOW if unused). There is also a burst mode pin (MODE)

that selects between interleaved and linear burst modes.

MODE may be tied HIGH, LOW or left unconnected if burst

is unused. The flow-through data-out (Q) is enabled by

OE#. WRITE cycles can be from one to four bytes wide as

controlled by the write control inputs.

OPTIONS

• Timing (Access/Cycle/MHz)

7.5ns/10ns/100 MHz

8.5ns/11ns/90 MHz

9ns/12ns/83 MHz

• Configurations

3.3V I/O

256K x 18

128K x 32

128K x 36

2.5V I/O

256K x 18

128K x 32

128K x 36

• Package

100-pin TQFP

MARKING

-10

-11

-12

MT55L256L18F

MT55L128L32F

MT55L128L36F

MT55L256V18F

MT55L128V32F

MT55L128V36F

• Part Number Example: MT55L256L18FT-11

4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM

MT55L256L18F.p65 – Rev. 9/99

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Micron Technology, Inc.

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