TECHNOLOGY, INC.
1 MEG x 16
EDO DRAM
MT4C1M16E5
MT4LC1M16E5
DRAM
FEATURES
• JEDEC- and industry-standard x16 timing, functions,
pinouts and packages
• High-performance CMOS silicon-gate process
• Single power supply (+3.3V
±0.3V
or 5V
±10%)
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#
(CBR), HIDDEN; optional Self Refresh
• BYTE WRITE access cycles
• 1,024-cycle refresh (10 row, 10 column addresses)
• Extended Data-Out (EDO) PAGE MODE access cycle
• 5V-tolerant inputs and I/Os on 3.3V devices
PIN ASSIGNMENT (Top View)
44/50-Pin TSOP
(DB-6)
Vcc
DQ1
DQ2
DQ3
DQ4
Vcc
DQ5
DQ6
DQ7
DQ8
NC
1
2
3
4
5
6
7
8
9
10
11
50
49
48
47
46
45
44
43
42
41
40
Vss
DQ16
DQ15
DQ14
DQ13
Vss
DQ12
DQ11
DQ10
DQ9
NC
42-Pin SOJ
(DA-7)
Vcc
DQ1
DQ2
DQ3
DQ4
Vcc
DQ5
DQ6
DQ7
DQ8
NC
NC
WE#
RAS#
NC
NC
A0
A1
A2
A3
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
Vss
DQ16
DQ15
DQ14
DQ13
Vss
DQ12
DQ11
DQ10
DQ9
NC
CASL#
CASH#
OE#
A9
A8
A7
A6
A5
A4
Vss
OPTIONS
• Voltages
3.3V
5V
• Packages
Plastic SOJ (400 mil)
Plastic TSOP (400 mil)
• Timing
50ns access
60ns access
70ns access (3.3V only)
• Refresh Rates
Standard Refresh (16ms period)
Self Refresh and (128ms period)
MARKING
LC
C
DJ
TG
-5
-6
-7
None
S
NC
NC
WE#
RAS#
NC
NC
A0
A1
A2
A3
Vcc
15
16
17
18
19
20
21
22
23
24
25
36
35
34
33
32
31
30
29
28
27
26
NC
CASL#
CASH#
OE#
A9
A8
A7
A6
A5
A4
Vss
Note:
The “#” symbol indicates signal is active LOW.
1 MEG x 16 EDO DRAM PART NUMBERS
PART NUMBER
MT4LC1M16E5DJ
MT4LC1M16E5DJS
MT4LC1M16E5TG
MT4LC1M16E5TGS
MT4C1M16E5DJ
MT4C1M16E5DJS
MT4C1M16E5TG
MT4C1M16E5TGS
V
CC
3.3V
3.3V
3.3V
3.3V
5V
5V
5V
5V
REFRESH
1K
1K
1K
1K
1K
1K
1K
1K
PACKAGE
400-SOJ
400-SOJ
400-TSOP
400-TSOP
400-SOJ
400-SOJ
400-TSOP
400-TSOP
REFRESH
Standard
Self
Standard
Self
Standard
Self
Standard
Self
• Part Number Example: MT4LC1M16E5TG-6
Note: The 1 Meg x 16 EDO DRAM base number differentiates the offerings in
one place -
MT4LC1M16E5.
The third field distinguishes the low voltage
offering: LC designates V
CC
= 3.3V and C designates V
CC
= 5V.
KEY TIMING PARAMETERS
SPEED
-5
-6
-7*
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
CAS
84ns
104ns
124ns
50ns
60ns
70ns
20ns
25ns
30ns
25ns
30ns
35ns
15ns
17ns
20ns
8ns
10ns
12ns
*3.3V version only.
GENERAL DESCRIPTION
The 1 Meg x 16 is a randomly accessed, solid-state memory
containing 16,777,216 bits organized in a x16 configuration.
The 1 Meg x 16 has both BYTE WRITE and WORD WRITE
access cycles via two CAS# pins (CASL# and CASH#).
1 Meg x 16 EDO DRAM
D52.pm5 – Rev. 3/97
These function like a single CAS# found on other DRAMs
in that either CASL# or CASH# will generate an internal
CAS#.
The CAS# function and timing are determined by the first
CAS# (CASL# or CASH#) to transition LOW and the last
CAS# to transition back HIGH. Using only one of the two
signals results in a BYTE WRITE cycle. CASL# transitioning
LOW selects an access cycle for the lower byte (DQ1-DQ8),
and CASH# transitioning LOW selects an access cycle for
the upper byte (DQ9-DQ16).
Each bit is uniquely addressed through the 20 address
bits during READ or WRITE cycles. These are entered 10
bits (A0 -A9) at a time. RAS# is used to latch the first 10 bits
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1997,
Micron Technology, Inc.
TECHNOLOGY, INC.
1 MEG x 16
EDO DRAM
GENERAL DESCRIPTION (continued)
and CAS#, the latter 10 bits. The CAS# function also deter-
mines whether the cycle will be a refresh cycle (RAS#
ONLY) or an active cycle (READ, WRITE or READ-WRITE)
once RAS# goes LOW.
The CASL# and CASH# inputs internally generate a
CAS# signal that functions like the single CAS# input on
other DRAMs. The key difference is each CAS# input
(CASL# and CASH#) controls its corresponding eight DQ
inputs during WRITE accesses. CASL# controls DQ1-DQ8,
and CASH# controls DQ9-DQ16. The two CAS# controls
give the 1 Meg x 16 both BYTE READ and BYTE WRITE
cycle capabilities.
A logic HIGH on WE# dictates READ mode, while a logic
LOW on WE# dictates WRITE mode. During a WRITE
cycle, data-in (D) is latched by the falling edge of WE or
CAS# (CASL# or CASH#), whichever occurs last. An EARLY
WRITE occurs when WE is taken LOW prior to either CAS#
falling. A LATE WRITE or READ-MODIFY-WRITE occurs
when WE falls after CAS# (CASL# or CASH#) was taken
LOW. During EARLY WRITE cycles, the data outputs (Q)
will remain High-Z, regardless of the state of OE#. During
LATE WRITE or READ-MODIFY-WRITE cycles, OE# must
be taken HIGH to disable the data outputs prior to applying
input data. If a LATE WRITE or READ-MODIFY-WRITE is
attempted while keeping OE# LOW, no write will occur,
and the data outputs will drive read data from the accessed
location.
RAS#
V IH
V IL
The 16 data inputs and 16 data outputs are routed through
16 pins using common I/O. Pin direction is controlled by
OE# and WE#.
PAGE ACCESS
PAGE operations allow faster data operations (READ,
WRITE or READ-MODIFY-WRITE) within a row address-
defined page boundary. The PAGE cycle is always initiated
with a row address strobed-in by RAS#, followed by a
column address strobed-in by CAS#. CAS# may be toggled-
in by holding RAS# LOW and strobing-in different column
addresses, thus executing faster memory cycles. Returning
RAS# HIGH terminates the PAGE MODE of operation.
EDO PAGE MODE
The 1 Meg x 16 provides EDO PAGE MODE, which is an
accelerated FAST PAGE MODE cycle. The primary advan-
tage of EDO is the availability of data-out even after CAS#
returns HIGH. EDO provides for CAS# precharge time
(
t
CP) to occur without the output data going invalid. This
elimination of CAS# output control provides for pipeline
READs.
FAST PAGE MODE DRAMs have traditionally turned
the output buffers off (High-Z) with the rising edge of
CAS#. EDO PAGE MODE DRAMs operate like FAST
CASL#/CASH#
ADDR
DQ V IOH
V IOL
, ,,,, ,,,,, ,,,,, ,,,,
,, ,, , ,
,
, , , ,
V IH
V IL
V IH
V IL
ROW
COLUMN (A)
COLUMN (B)
COLUMN (C)
COLUMN (D)
OPEN
V IH
V IL
OE#
,,
VALID DATA (A)
t OD
VALID DATA (A)
t OES
t OE
,,, ,,
VALID DATA (B)
t OD
t OEHC
VALID DATA (C)
t OD
,
VALID DATA (D)
t OEP
The DQs go back to
Low-Z if
t
OES is met.
The DQs remain High-Z
until the next CAS# cycle
if
t
OEHC is met.
The DQs remain High-Z
until the next CAS# cycle
if
t
OEP is met.
Figure 1
OE# CONTROL OF DQs
1 Meg x 16 EDO DRAM
D52.pm5 – Rev. 3/97
,
,
,,
,,
DON’T CARE
UNDEFINED
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1997,
Micron Technology, Inc.
TECHNOLOGY, INC.
1 MEG x 16
EDO DRAM
EDO PAGE MODE
(continued)
PAGE MODE DRAMs, except data will remain valid or
become valid after CAS# goes HIGH during READs, pro-
vided RAS# and OE# are held LOW. If OE# is pulsed while
RAS# and CAS# are LOW, data will toggle from valid data
to High-Z and back to the same valid data. If OE# is toggled
or pulsed after CAS# goes HIGH while RAS# remains
LOW, data will transition to and remain High-Z (refer to
Figure 1). WE# can also perform the function of disabling
the output drivers under certain conditions, as shown in
Figure 2.
During an application, if the DQ outputs are wire OR’d,
OE# must be used to disable idle banks of DRAMs. Alter-
natively, pulsing WE# to the idle banks during CAS# HIGH
time will also High-Z the outputs. Independent of OE#
control, the outputs will disable after
t
OFF, which is refer-
enced from the rising edge of RAS# or CAS#, whichever
occurs last.
The 1 Meg x 16 may be viewed as two 1 Meg x 8 DRAMs
that have common input controls, with the exception of the
CAS# inputs. Figure 3 illustrates the BYTE WRITE and
WORD WRITE cycles.
Additionally, both bytes must always be of the same
mode of operation if both bytes are active. A CAS# precharge
must be satisfied prior to changing modes of operation
between the upper and lower bytes. For example, an EARLY
WRITE on one byte and a LATE WRITE on the other byte
are not allowed during the same cycle. However, an EARLY
WRITE on one byte and a LATE WRITE on the other byte,
after a CAS# precharge has been satisfied, are permissible.
REFRESH
Preserve correct memory cell data by maintaining power
and executing any RAS# cycle (READ, WRITE) or RAS#
refresh cycle (RAS#-ONLY, CBR or HIDDEN) so that all
1,024 combinations of RAS# addresses are executed within
t
REF (MAX), regardless of sequence. The CBR, Extended
and Self Refresh cycles will invoke the internal refresh
counter for automatic RAS# addressing.
The optional Self Refresh mode is available on the
MT4LC1M16E5 S. The “S” option allows the user a dynamic
refresh, data retention mode at the extended refresh period
BYTE ACCESS CYCLE
The BYTE WRITEs and BYTE READs are determined by
the use of CASL# and CASH#. Enabling CASL# selects a
lower BYTE access (DQ1-DQ8). Enabling CASH# selects an
upper BYTE access (DQ9-DQ16). Enabling both CASL#
and CASH# selects a WORD WRITE cycle.
RAS#
CASL#/CASH#
ADDR
DQ V IOH
V IOL
, ,,,,,, ,,, , ,,,,
,, ,,
,
,
, , , ,
,,
,
,,
V IH
V IL
V IH
V IL
V IH
V IL
ROW
COLUMN (A)
COLUMN (B)
COLUMN (C)
COLUMN (D)
OPEN
V IH
V IL
V IH
V IL
WE#
,,
VALID DATA (A)
t
WHZ
t WPZ
,
VALID DATA (B)
INPUT DATA (C)
t WHZ
,,
OE#
The DQs go to High-Z if WE# falls, and if
t
WPZ is met,
will remain High-Z until CAS# goes LOW with
WE# HIGH (i.e., until a READ cycle is initiated).
WE# may be used to disable the DQs to prepare
for input data in an EARLY WRITE cycle. The DQs
will remain High-Z until CAS# goes LOW with
WE# HIGH (i.e., until a READ cycle is initiated).
Figure 2
WE# CONTROL OF DQs
1 Meg x 16 EDO DRAM
D52.pm5 – Rev. 3/97
,,
,,
,
,,
DON’T CARE
UNDEFINED
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1997,
Micron Technology, Inc.
TECHNOLOGY, INC.
1 MEG x 16
EDO DRAM
REFRESH
(continued)
of 128ms, i.e., 125µs per row when using distributed CBR
refreshes. The “S” option also allows the user the choice of
a fully static, low-power data retention mode. The optional
Self Refresh feature is initiated by performing a CBR Re-
fresh cycle and holding RAS# LOW for the specified
t
RASS.
The Self Refresh mode is terminated by driving
RAS# HIGH for a minimum time of
t
RPS. This delay allows
for the completion of any internal refresh cycles that may be
in process at the time of the RAS# LOW-to-HIGH transition.
If the DRAM controller uses a distributed refresh sequence,
a burst refresh is not required upon exiting Self Refresh.
However, if the DRAM controller utilizes a RAS#-ONLY or
burst refresh sequence, all 1,024 rows must be refreshed
within the average internal refresh rate, prior to the resump-
tion of normal operation.
STANDBY
Returning RAS# and CAS# HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
The chip is preconditioned for the next cycle during the
RAS# HIGH time.
WORD WRITE
RAS#
LOWER BYTE WRITE
CASL#
CASH#
WE#
LOWER BYTE
(DQ1-DQ8)
OF WORD
STORED
DATA
1
1
0
1
1
1
1
1
INPUT
DATA
0
0
1
0
0
0
0
0
INPUT
DATA
STORED STORED
DATA
DATA
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
INPUT
DATA
1
1
0
1
1
1
1
1
INPUT
DATA
STORED
DATA
1
1
0
1
1
1
1
1
UPPER BYTE
(DQ9-DQ16)
OF WORD
0
1
0
1
0
0
0
0
X
X
X
X
X
X
X
X
1
0
1
0
1
1
1
1
1
0
1
0
1
1
1
1
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
X
ADDRESS 1
1
0
1
0
1
1
1
1
ADDRESS 0
X = NOT EFFECTIVE (DON'T CARE)
Figure 3
WORD AND BYTE WRITE EXAMPLE
1 Meg x 16 EDO DRAM
D52.pm5 – Rev. 3/97
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1997,
Micron Technology, Inc.
TECHNOLOGY, INC.
1 MEG x 16
EDO DRAM
FUNCTIONAL BLOCK DIAGRAM
WE#
CASL#
CASH#
DQ1
16
NO. 2 CLOCK
GENERATOR
DATA-OUT
BUFFER
10
CAS#
DATA-IN BUFFER
DQ16
10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
10
COLUMN
ADDRESS
BUFFER
REFRESH
CONTROLLER
COLUMN
DECODER
16
1024
OE#
16
SENSE AMPLIFIERS
I/O GATING
REFRESH
COUNTER
10
ROW
DECODER
ROW
ADDRESS
BUFFERS (10)
1024 x 1024 x 16
MEMORY
ARRAY
1024 x 16
10
1024
RAS#
NO. 1 CLOCK
GENERATOR
Vcc
Vss
1 Meg x 16 EDO DRAM
D52.pm5 – Rev. 3/97
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1997,
Micron Technology, Inc.
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