IS49NLC96400-33BLI datasheet, PDF

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IS49NLC96400-33BLI: DescriptionDDR DRAM, 64MX9, 3.3ns, CMOS, PBGA144, 11 X 18.50 MM, LEAD FREE, FBGA-144; Categorystorage storage; File Size1MB，35 Pages; ManufacturerIntegrated Silicon Solution ( ISSI ); Environmental Compliance

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IS49NLC96400-33BLI Overview

DDR DRAM, 64MX9, 3.3ns, CMOS, PBGA144, 11 X 18.50 MM, LEAD FREE, FBGA-144

IS49NLC96400-33BLI Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Integrated Silicon Solution ( ISSI )
Parts packaging code	BGA
package instruction	TBGA, BGA144,12X18,40/32
Contacts	144
Reach Compliance Code	compliant
ECCN code	EAR99
Factory Lead Time	13 weeks 6 days
access mode	MULTI BANK PAGE BURST
Maximum access time	3.3 ns
Other features	AUTO REFRESH
Maximum clock frequency (fCLK)	300 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B144
length	18.5 mm
memory density	603979776 bit
Memory IC Type	DDR DRAM
memory width	9
Number of functions	1
Number of ports	1
Number of terminals	144
word count	67108864 words
character code	64000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	64MX9
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TBGA
Encapsulate equivalent code	BGA144,12X18,40/32
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE
power supply	1.5/1.8,1.8,2.5 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Continuous burst length	2,4,8
Maximum standby current	0.048 A
Maximum slew rate	0.819 mA
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	11 mm

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IS49NLC96400,IS49NLC18320,IS49NLC36160

576Mb (x9, x18, x36) Common I/O RLDRAM



2 Memory

FEATURES



400MHz DDR operation (800Mb/s/pin data rate)

28.8Gb/s peak bandwidth (x36 at 400 MHz clock

frequency)

Reduced cycle time (15ns at 400MHz)

32ms refresh (16K refresh for each bank; 128K refresh

command must be issued in total each 32ms)

8 internal banks

Non-multiplexed addresses (address multiplexing option

available)

SRAM-type interface

Programmable READ latency (RL), row cycle time, and

burst sequence length

Balanced READ and WRITE latencies in order to optimize

data bus utilization

Data mask signals (DM) to mask signal of WRITE data; DM

is sampled on both edges of DK.



Differential input clocks (CK, CK#)

Differential input data clocks (DKx, DKx#)

On-die DLL generates CK edge-aligned data and output

data clock signals

Data valid signal (QVLD)

HSTL I/O (1.5V or 1.8V nominal)

25-60Ω matched impedance outputs

2.5V V

EXT

, 1.8V V

, 1.5V or 1.8V V

DDQ

I/O

On-die termination (ODT) R

IEEE 1149.1 compliant JTAG boundary scan

Operating temperature:

Commercial

= 0° to +95°C; T

= 0°C to +70°C),

Industrial

= -40°C to +95°C; T

= -40°C to +85°C)

JUNE 2016



OPTIONS



Package:



144-ball FBGA (leaded)



144-ball FBGA (lead-free)



144-ball WBGA (lead-free)

Configuration:



64Mx9



32Mx18



16Mx36

Clock Cycle Timing:



Speed Grade

-25E

2.5

-25

2.5

-33

3.3

-5

Unit

notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the

latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can

reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such

applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

RLDRAM



is a registered trademark of Micron Technology, Inc.

Integrated Silicon Solution, Inc. – www.issi.com –

Rev. A1, 06/06/2016

IS49NLC96400,IS49NLC18320,IS49NLC36160

1.4 Ball Descriptions

Symbol

BA*

CK, CK#

CS#

DQ*

Type

Input

I/O

Description

Address inputs: Defines the row and column addresses for READ and WRITE operations. During a MODE

CK.

Bank address inputs: Selects to which internal bank a command is being applied to.

Input clock: CK and CK# are differential input clocks. Addresses and commands are latched on the rising

edge of CK. CK# is ideally 180 degrees out of phase with CK.

Chip select: CS# enables the command decoder when LOW and disables it when HIGH. When the

command decoder is disabled, new commands are ignored, but internal operations continue.

Data input: The DQ signals form the data bus. During READ commands, the data is referenced to both

edges of QK*. During WRITE commands, the data is sampled at both edges of DK.

Input data clock: DK* and DK*# are the differential input data clocks. All input data is referenced to

both edges of DK*. DK*# is ideally 180 degrees out of phase with DK*. For the x36 device, DQ0–DQ17

are referenced to DK0 and DK0# and DQ18–DQ35 are referenced to DK1 and DK1#. For the x9 and x18

devices, all DQ* are referenced to DK and DK#. All DK* and DK*# pins must always be supplied to the

device.

Input data mask: The DM signal is the input mask signal for WRITE data. Input data is masked when DM

is sampled HIGH. DM is sampled on both edges of DK (DK1 for the x36 configuration). Tie signal to

ground if not used.

IEEE 1149.1 clock input: This ball must be tied to V

if the JTAG function is not used.

IEEE 1149.1 test inputs: These balls may be left as no connects if the JTAG function is not used.

Command inputs: Sampled at the positive edge of CK, WE# and REF# define (together with CS#) the

command to be executed.

Input reference voltage: Nominally V

DDQ

/2. Provides a reference voltage for the input buffers.

External impedance (25–60Ω): This signal is used to tune the device outputs to the system data bus

impedance. DQ output impedance is set to 0.2 × RQ, where RQ is a resistor from this signal to ground.

Connecting ZQ to GND invokes the minimum impedance mode.

Output data clocks: QK* and QK*# are opposite polarity, output data clocks. They are free running, and

during READs, are edge-aligned with data output from the memory. QK*# is ideally 180 degrees out of

phase with QK*. For the x36 device, QK0 and QK0# are aligned with DQ0-DQ17, and QK1 and QK1# are

aligned with DQ18-DQ35. For the x18 device, QK0 and QK0# are aligned with DQ0-DQ8, while QK1 and

QK1# are aligned with Q9-Q17. For the x9 device, all DQs are aligned with QK0 and QK0#.

Data valid: The QVLD pin indicates valid output data. QVLD is edge-aligned with QK* and QK*#.

IEEE 1149.1 test output: JTAG output. This ball may be left as no connect if the JTAG function is not

used.

Power supply: Nominally, 1.8V.

DQ power supply: Nominally, 1.5V or 1.8V. Isolated on the device for improved noise immunity.

Power supply: Nominally, 2.5V.

Ground.

DQ ground: Isolated on the device for improved noise immunity.

Power supply: Isolated termination supply. Nominally, V

DDQ

/2.

Reserved for future use: This signal is not connected and can be connected to ground.

Do not use: These balls may be connected to ground. Note that if ODT is enabled, these pins are High-Z.

No function: These balls can be connected to ground.

DK*, DK*#

Input

TCK

TMS,TDI

WE#, REF#

REF

Input

I/O

QK*, QK*#

Output

QVLD

TDO

DDQ

EXT

SSQ

A22

DNU

Output

Supply

Integrated Silicon Solution, Inc. – www.issi.com –

Rev. A1, 06/06/2016

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