EEWORLDEEWORLDEEWORLD

Part Number

Search

SM364TCSMB3WI15

Description
Cache Tag SRAM Module, 32KX64, CMOS, DIMM-160
Categorystorage    storage   
File Size30KB,5 Pages
ManufacturerSMART Modular Technology Inc
Download Datasheet Parametric View All

SM364TCSMB3WI15 Overview

Cache Tag SRAM Module, 32KX64, CMOS, DIMM-160

SM364TCSMB3WI15 Parametric

Parameter NameAttribute value
MakerSMART Modular Technology Inc
Parts packaging codeDIMM
package instruction,
Contacts160
Reach Compliance Codeunknown
ECCN code3A991.B.2.A
Other features8K X 8 TAG
JESD-30 codeR-XDMA-N160
memory density2097152 bit
Memory IC TypeCACHE TAG SRAM MODULE
memory width64
Number of functions1
Number of terminals160
word count32768 words
character code32000
Operating modeSYNCHRONOUS
organize32KX64
Package body materialUNSPECIFIED
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
Parallel/SerialPARALLEL
Certification statusNot Qualified
Maximum supply voltage (Vsup)3.63 V
Minimum supply voltage (Vsup)2.97 V
Nominal supply voltage (Vsup)3.3 V
surface mountNO
technologyCMOS
Terminal formNO LEAD
Terminal locationDUAL
SM364TCSMB3UI15
Modular Technologies
SMART
February 1997
Rev 0
SM364TCSMB3UI15
256KByte (32Kx64) Synchronous Secondary Cache SRAM Module
General Description
The SM364TCSMB3UI15 is a high performance, 256
Kilobyte synchronous secondary cache SRAM module for
use with Intel Triton Chipset. It is organized as 32K
words by 64 bits, in a 160-pin, dual readout, leadless,
double-in-line memory module (DIMM) package.
The module utilizes two CMOS 32Kx32 static RAMs for
data and two 8Kx8 static RAM for tag in surface mount
packages on an epoxy laminate substrate. Each device is
accompanied by decoupling capacitors for improved noise
immunity.
Control lines provided are such that byte write control is
possible.
Functional Diagram
CWE4#~CWE7#
CWE0#~CWE3#
CADS#
ADSP#
CADV#
CCS#
COE#
BWE#
GWE#
CLK0
VCC3
ECS1#, ECS2#
A3
A4
A5~A17
MODE
BW1#~BW4#
ADSC#
ADSP#
ADV#
CS#
OE#
BWE#
GWE#
CLK
32Kx32
CS2
SRAM
CS2#
A0
A1
A2~A14
MODE
D0~D31
BW1#~BW4#
ADSC#
ADSP#
ADV#
CS#
OE#
BWE#
GWE#
CLK
32Kx32
CS2
SRAM
CS2#
A0
A1
A2~A14
MODE
D32~D63
Features
COASt 3.1 compliant
High Density : 256KByte
Fast Cycle Time of 15ns (max.)
Low Power (typical) :
Active :
3.1W
Standby :
440mW - TTL/LVTTL
220W - CMOS
TTL-compatible inputs and outputs
Separate power and ground planes
Dual power supplies : 5V+10%
3.3V±10%
Height : 1.250"
DATA RAMs
D0~D63
A0~A12
A0~A12
TAG RAMs
8Kx8
8Kx8
TWE#
WE# SRAM
WE# SRAM
ECS1#, ECS2#
CE1#
CE1#
Notes:
1. All the data lines are terminated using
(Data RAMs)
V
CC3
V
SS
series resistors.
TIO0~TIO7
TIO8~TIO10
2. MODE has a pull-up resistor of 4.7KΩ.
3. TIO8, TIO9 have pull-up resistors and TIO10
(Tag RAMs)
V
CC5
V
SS
TIO0~TIO10
has a pull-down resistor of 8.2KΩ.
4. All unused tag bits have pull-down resistors of
Decoupling capacitors
150KΩ.
to all devices
(All specifications of this device are subject to change without notice.)
Corporate Headquarters:
4305 Cushing Pkwy., Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
36 Linford Forum, Rockingham Dr., Linford Wood, Milton Keynes, MK14 6LY, UK • Tel: + 44-1908 234030 • Fax: + 44-1908-234191
Asia/Pacific:
Suite 6A, 64 Canning Hwy., Victoria Park, Perth, WA 6106, Australia • Tel: + 61-9-361-9705 • Fax: + 61-9-361-9715
1

Technical ResourceMore

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2808  2421  122  47  1638  57  49  3  1  33 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号