32C408BRPFS-25 datasheet, PDF - EEWORLD Datasheet

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32C408BRPFS-25: DescriptionStandard SRAM, 512KX8, 25ns, CMOS, RAD PAK, LDFP-36; Categorystorage storage; File Size108KB，11 Pages; ManufacturerMaxwell Technologies Inc.

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32C408BRPFS-25 Overview

Standard SRAM, 512KX8, 25ns, CMOS, RAD PAK, LDFP-36

32C408BRPFS-25 Parametric

Parameter Name	Attribute value
Maker	Maxwell Technologies Inc.
Parts packaging code	DFP
package instruction	DFP,
Contacts	36
Reach Compliance Code	unknown
ECCN code	3A001.A.2.C
Maximum access time	25 ns
JESD-30 code	R-XDFP-F36
length	23.622 mm
memory density	4194304 bit
Memory IC Type	STANDARD SRAM
memory width	8
Number of functions	1
Number of terminals	36
word count	524288 words
character code	512000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	512KX8
Package body material	UNSPECIFIED
encapsulated code	DFP
Package shape	RECTANGULAR
Package form	FLATPACK
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum seat height	3.7592 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	FLAT
Terminal pitch	1.27 mm
Terminal location	DUAL
width	16.383 mm

32C408BRPFS-25 Preview

32C408B

4 Megabit (512K x 8-Bit) SRAM

A13

A12

A11

A10

I/O1

I/O2

Vcc

Vss

I/O3

I/O4

A18

A17

A16

A15

I/O8

I/O7

ROW

DECODER

MEMORY MATRIX

1024 ROWS x 4096 COLUMNS

DQ0

32C408B

Vss

Vcc

I/O6

I/O5

A14

A13

A12

A11

A10

DQ7

COLUMN I/O

INPUT

DATA

CONTROL

COLUMN DECODER

A18

A17

A16

A15

A14

DQ0

Memory

DQ7

Logic Diagram

EATURES

• 512k x 8-bit CMOS architecture

• R

-P

® technology hardened against natural space radi-

ation

• Total dose hardness:

- > 100 krad (Si), depending upon space mission

• Single event effect:

- SEL

: > 68 MeV/mg/cm

- SEU

: < 3MeV/mg/cm

- SEU saturated cross section: 6E-9 cm

/bit

• Package:

-36 pin R

-P

® flat pack

• Fast propagation time:

-20, 25, 30 ns maximum access time

• Single 5V + 10% power supply

• Low power dissipation:

- Standby: 60mA (TTL); 10mA (CMOS)

- Operating: 180 mA (20 ns); 170 mA (25 ns); 160 mA (30

ns)

• TTL compatible inputs and outputs

• Fully static operation

- No clock or refresh required

• Three state outputs

ESCRIPTION

Maxwell Technologies’ 32C408B high-speed 4 Megabit SRAM

microcircuit features a greater than 100 krad (Si) total dose

tolerance, depending upon space mission. Using R

-P

packaging technology, the 32C408B realizes higher density,

higher performance and lower power consumption, and is well

suited for high-speed system application. Its fully static design

eliminates the need for external clocks, while the CMOS cir-

cuitry reduces power consumption and provides higher reli-

ability. The 32C408B is equipped with eight common input/

output lines, chip select and output enable, allowing for

greater system flexibility and eliminating bus contention.

Maxwell Technologies' patented R

-P

packaging technol-

ogy incorporates radiation shielding in the microcircuit pack-

age. In a GEO orbit, R

-P

can provides true greater than

100 krad (Si) total radiation dose tolerance; dependent upon

space mission. The patented radiation-hardened R

-P

technology incorporates radiation shielding in the microcircuit

package. It eliminates the need for box shielding while provid-

ing the required radiation shielding for a lifetime in orbit or a

space mission. This product is available with packaging and

screening up to Class S.

05.02.02 Rev 7

All data sheets are subject to change without notice

(858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com

4 Megabit (512K x 8-Bit) SRAM

ABLE

1. 32C408B A

BSOLUTE

AXIMUM

ATINGS

ARAMETER

Voltage on any pin relative to V

Voltage on V

supply relative to V

Power Dissipation

Storage Temperature

Operating Temperature

YMBOL

, V

OUT

-0.5

-65

-55

32C408B

+0.5

7.0

1.0

+150

+125

NIT

ABLE

2. 32C408B R

ECOMMENDED

PERATING

ONDITIONS

ARAMETER

Supply Voltage

Ground

Input High Voltage

Input Low Voltage

Thermal Impedance

1. V

(max) = V

+ 2.0V ac(pulse width < 10ns) for I < 20mA.

2. V

(min) = -2.0V ac(pulse width < 10ns) for I < 20mA.

YMBOL

4.5

2.2

-0.5

5.5

+0.5

0.8

0.63

NIT

°C/W

Memory

ABLE

3. 32C408B DC E

LECTRICAL

HARACTERISTICS

=5V +/- 10%, T

= -55

+1‘25C, U

NLESS

TERWISE

PECIFIED

ARAMETER

Input Leakage Current

Output Leakage Current

Output Low Voltage

Output High Voltage

ONDITION

= V

to V

CS=V

or OE=V

or WE=V

OUT

to V

= 8mA

= -4mA

YMBOL

UBGROUPS

1, 2, 3

SB1

I/O

1, 2, 3

-2

2.4

180

170

160

0.4

NIT

µA

Average Operating Cur-

Min cycle, 100% Duty, CS=V

OUT

=0mA, V

= V

or V

rent

-20

-25

-30

Standby Power Supply

Current

Input Capacitance

Output Capacitance

1. Guaranteed by Design

CS = V

f = 0MHz, CS > V

- 02V, V

- 0.2V or V

< 0.2V

= 0V, f = 1MHz, T

= 25 °C.

I/O

= 0V

05.02.02 Rev 7

All data sheets are subject to change without notice

4 Megabit (512K x 8-Bit) SRAM

ABLE

4. 32C408B AC C

HARACTERISTICS FOR

EAD

YCLE

=5V +/- 10%, T

= -55

+1‘25C, U

NLESS

TERWISE

PECIFIED

ARAMETER

Read Cycle Time

-20

-25

-30

Address Access Time

-20

-25

-30

Chip Select Access Time

-20

-25

-30

Output Enable to Output Valid

-20

-25

-30

Chip Select to Output in Low-Z

-20

-25

-30

Output Enable to Output in Low-Z

-20

-25

-30

Chip Deselect to Output in High-Z

-20

-25

-30

Output Disable to Output in High-Z

-20

-25

-30

Output Hold from Address Change

-20

-25

-30

Chip Select to Power Up Time

-20

-25

-30

Chip Select to Power Down Time

-20

-25

-30

YMBOL

UBGROUPS

9, 10, 11

OLZ

9, 10, 11

OHZ

9, 10, 11

32C408B

NIT

Memory

05.02.02 Rev 7

All data sheets are subject to change without notice

4 Megabit (512K x 8-Bit) SRAM

ABLE

5. 32408B F

UNCTIONAL

ESCRIPTION 1

1. X = don’t care.

ODE

Not Select

Output Disable

Read

Write

I/O P

High-Z

OUT

32C408B

UPPLY

URRENT

, I

SB1

ABLE

6. 32C408B AC C

HARACTERISTICS FOR

RITE

YCLE

=5V +/- 10%, T

= -55

+1‘25C, U

NLESS

TERWISE

PECIFIED

ARAMETER

Write Cycle Time

-20

-25

-30

Chip Select to End of Write

-20

-25

-30

Address Setup Time

-20

-25

-30

Address Valid to End of Write

-20

-25

-30

Write Pulse Width (OE High)

-20

-25

-30

Write Recovery Time

-20

-25

-30

Write to Output in High-Z

-20

-25

-30

YMBOL

UBGROUPS

9, 10, 11

WHZ

9, 10, 11

NIT

Memory

05.02.02 Rev 7

All data sheets are subject to change without notice

4 Megabit (512K x 8-Bit) SRAM

ABLE

6. 32C408B AC C

HARACTERISTICS FOR

RITE

YCLE

=5V +/- 10%, T

= -55

+1‘25C, U

NLESS

TERWISE

PECIFIED

ARAMETER

Write Pulse Width(OE Low)

-20

-25

-30

Data to Write Time Overlap

-20

-25

-30

End Write to Output Low-Z 1

-20

-25

-30

Data Hold from Write Time

-20

-25

-30

YMBOL

WP1

UBGROUPS

9, 10, 11

tOW

9, 10, 11

32C408B

NIT

Memory

IGURE

1. T

IMING

AVEFORM OF

RITE

YCLE

(1) (OE C

LOCK

)

05.02.02 Rev 7

All data sheets are subject to change without notice

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