IDT74FCT299A
FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER
COMMERCIAL TEMPERATURE RANGE
FAST CMOS
8-INPUT UNIVERSAL
SHIFT REGISTER
FEATURES:
DESCRIPTION:
IDT74FCT299A
• IDT74FCT299A 25% faster than FAST
• Equivalent to FAST output drive over full temperature and
voltage supply extremes
• I
OL
= 48mA
• CMOS power levels (1mW typ. static)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than FAST (5µA max.)
µ
• 8-input universal shift register
• Available in SOIC package
The IDT74FCT299A is built using an advanced dual metal CMOS
technology. The IDT74FCT299A is an 8-input universal shift/storage
register with 3-state outputs. Four modes of operation are possible: hold
(store), shift left, shift right and load data. The parallel load inputs and flip-
flop outputs are multiplexed to reduce the total number of package pins.
Additional outputs are provided for flip-flops Q
0
and Q
7
to allow easy serial
cascading. A separate active low Master Reset is used to reset the register.
FUNCTIONAL BLOCK DIAGRAM
S
1
S
0
DS
7
DS
0
CP
D
C
D
Q
Q
0
MR
OE
1
OE
2
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
CP
C
D
Q
D
CP
C
D
Q
D
CP
C
D
Q
D
CP
C
D
Q
D
CP
C
D
Q
D
CP
C
D
Q
D
CP
C
D
Q
Q
7
D
CP
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
JUNE 2002
DSC-4604/5
© 2002 Integrated Device Technology, Inc.
IDT74FCT299A
FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Terminal Voltage with Respect to GND
Operating Temperature
Temperature under BIAS
Storage Temperature
Power Dissipation
DC Output Current
Max
–0.5 to +7
–0.5 to V
CC
0 to +70
–55 to +125
–55 to +125
0.5
120
Unit
V
V
°C
°C
°C
W
mA
V
TERM
(2)
Terminal Voltage with Respect to GND
S
0
OE
1
OE
2
I/O
6
I/O
4
I/O
2
I/O
0
Q
0
MR
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SOIC
TOP VIEW
V
CC
S
1
DS
7
Q
7
I/O
7
I/O
5
I/O
3
I/O
1
CP
DS
0
V
TERM
(3)
T
A
T
BIAS
T
STG
P
T
I
OUT
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
2. Input and Vcc terminals only.
3. Output and I/O terminals only.
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
6
8
Max.
10
12
Unit
pF
pF
NOTE:
1. This parameter is measured at characterization but not tested.
PIN DESCRIPTION
Pin Names
CP
DS
0
DS
7
S
0
, S
1
MR
OE
1
,
OE
2
I/O
0
- I/O
7
Q
0
, Q
7
Description
Clock Pulse Input (Active Edge Rising)
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Mode Select Inputs
Asynchronous Master Reset Input (Active LOW)
3-State Output Enable Inputs (Active LOW)
Parallel Data Inputs or 3-State Parallel Outputs
Serial Outputs
FUNCTION TABLE
(1)
MR
L
H
H
H
H
Inputs
S
1
S
0
X
X
H
H
L
H
H
L
L
L
CP
X
↑
↑
↑
X
Response
Asynchronous Reset Q
0
- Q
7
= LOW
Parallel Load: I/On - Qn
Shift Right: DS
0
- Qo, Q
0
- Q
1
, etc.
Shift Left: DS
7
- Q
7
, Q
7
- Q
6
, etc.
Hold
NOTE:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
↑
= LOW-to-HIGH clock transition
2
IDT74FCT299A
FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: V
LC
= 0.2V; V
HC
= V
CC
– 0.2V
Commercial: T
A
= 0°C to +70°C, V
CC
= 5.0V ± 5%
Symbol
V
IH
V
IL
I
IH
I
IL
I
IH
I
IL
V
IK
I
OS
V
OH
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
(Except I/O Pins)
Input LOW Current
(Except I/O Pins)
Input HIGH Current
(I/O Pins Only)
Input LOW Current
(I/O Pins Only)
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
Vcc = Min., I
N
= –18mA
Vcc = Max. , V
O
= GND
Vcc = 3V, V
IN
= V
LC
or V
HC
, I
OH
= –32µA
Vcc = Min.
V
IN
= V
IH
or V
IL
V
OL
Output LOW Voltage
Vcc = Min.
V
IN
= V
IH
or V
IL
I
OH
= –300µA
I
OH
= –15mA
I
OL
= 300µA
I
OL
= 48mA
(3)
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
I
= V
CC
V
I
= 2.7V
V
I
= 0.5V
V
I
= GND
V
CC
= Max.
V
I
= V
CC
V
I
= 2.7V
V
I
= 0.5V
V
I
= GND
Min.
2
—
—
—
—
—
—
—
—
—
—
–60
V
HC
V
HC
2.4
—
—
—
Typ.
(2)
—
—
—
—
—
—
—
—
—
—
–0.7
–120
V
CC
V
CC
4.3
GND
GND
0.3
Max.
—
0.8
5
5
(4)
–5
(4)
–5
15
15
(4)
Unit
V
V
µA
µA
–15
(4)
–15
–1.2
—
—
—
—
V
LC
V
LC(4)
0.5
V
V
mA
V
Vcc = 3V, V
IN
= V
LC
or V
HC
, I
OL
= 300µA
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
3
IDT74FCT299A
FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER
COMMERCIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
V
LC
= 0.2V; V
HC
= V
CC
– 0.2V
Symbol
I
CC
∆I
CC
I
CCD
Parameter
Quiescent Power Supply
Current
Quiescent Power Supply
Current TTL Inputs HIGH
Dynamic Power Supply
Current
(4)
Test Conditions
(1)
Vcc = Max.
V
IN
≥
V
HC
; V
IN
≤
V
LC
Vcc = Max.
V
IN
= 3.4V
(3)
Vcc = Max.
Outputs Open
OE
1
=
OE
2
= GND
MR
= V
CC
S
0
= S
1
= V
CC
DS
0
= DS
1
= GND
One Input Toggling
50% Duty Cycle
Vcc = Max.
Outputs Open
f
CP
= 10MHz
50% Duty Cycle
OE
1
=
OE
2
= GND
MR
= V
CC
S
0
= S
1
= V
CC
DS
0
= DS
7
= GND
One Bit Toggling
at f
i
= 5MHz
50% Duty Cycle
Vcc = Max.
Outputs Open
f
CP
= 10MHz
50% Duty Cycle
OE
1
=
OE
2
= GND
MR
= V
CC
S
0
= S
1
= V
CC
DS
0
= DS
7
= GND
Eight Bits Toggling
at f
i
= 2.5MHz
50% Duty Cycle
V
IN
≥
V
HC
V
IN
≤
V
LC
Min.
—
—
—
Typ.
(2)
0.2
0.5
0.15
Max.
1.5
2
0.25
Unit
mA
mA
mA/MHz
I
C
Total Power Supply
Current
(6)
V
IN
≥
V
HC
V
IN
≤
V
LC
(FCT)
—
1.7
4
mA
V
IN
= 3.4V
V
IN
= GND
—
2.2
6
V
IN
≥
V
HC
V
IN
≤
V
LC
(FCT)
—
4
7.8
(5)
V
IN
= 3.4V
V
IN
= GND
—
6.2
16.8
(5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V); all other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + f
i
N
i
)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
4
IDT74FCT299A
FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER
COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
H
t
SU
t
H
t
W
t
W
t
REM
Parameter
Propagation Delay
CP to Q
0
or Q
7
Propagation Delay
CP to I/O
n
Propagation Delay
MR
to Q
0
or Q
7
Propagation Delay
MR
to I/O
n
Output Enable Time
OE
n
to I/O
n
Output Disable Time
OE
n
to I/O
n
Set-up Time HIGH or LOW
S
0
or S
1
to CP
Hold Time HIGH or LOW
S
0
or S
1
to CP
Set-up Time HIGH or LOW
I/O
n
, DS
0,
or DS
7
to CP
Hold Time HIGH or LOW
I/O
n
, DS
0
, or DS
7
to CP
CP Pulse Width HIGH or LOW
MR
Pulse Width LOW
Recovery Time
MR
to CP
Condition
(1)
C
L
= 50pF
R
L
= 500Ω
Min.
(2)
2
2
2
2
1.5
1.5
3.5
1
4
1.5
5
5
5
Max.
7.2
7.2
7.2
8.7
6.5
6
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
5
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