Mobile Intel® Celeron™ Processor
(0.18µ) in BGA2 and Micro-PGA2
Packages
at 700 MHz, 650 MHz, 600 MHz, 550 MHz, 500 MHz, 450 MHz,
Low-voltage 500 MHz, and Low-voltage 400A MHz
Datasheet
Product Features
!
Processor core/bus speeds:
!
700/100 MHz at 1.6V
650/100 MHz at 1.6V
600/100 MHz at 1.6V
550/100 MHz at 1.6V
500/100 MHz at 1.6V
450/100 MHz at 1.6V
500/100 MHz at 1.35V
!
400A/100 MHz at 1.35V
Supports the Intel Architecture with Dynamic
Execution
!
On-die primary 16-Kbyte instruction cache
and 16-Kbyte write-back data cache
On-die second level cache (128-Kbyte)
Integrated GTL+ termination
On-die thermal diode
Integrated math co-processor
Fully compatible with previous Intel
microprocessors
—
—
—
Binary compatible with all applications
Support for MMX™ technology
Support for Streaming SIMD
Extensions
Quick Start and Deep Sleep modes
provide low-power dissipation
Power Management Features
—
!
!
!
!
!
!
BGA2 and Micro-PGA2 packaging
technologies
—
—
Supports thin form factor notebook
designs
Exposed die enables more efficient
heat dissipation
Datasheet
Order Number- 245417- 004
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel mobile Celeron™ processor may contain design defects or errors known as errata that may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling1-800-548-
4725 or by visiting Intel’s web site at http://www.intel.com
Copyright © Intel Corporation, 1998, 1999, 2000.
*Other brands and names are the property of their respective owners.
®
Datasheet
Order#-XXX
Mobile Intel® Celeron™ Processor (0.18µ) in BGA2 and Micro-PGA2 Packages
at 700 MHz, 650 MHz, 600 MHz, 550 MHz, 500 MHz, 450 MHz,
Low-voltage 500 MHz, and Low-voltage 400A MHz
Contents
1.0
Introduction.....................................................................................................................................1
1.1
1.2
1.3
2.0
2.1
Overview.................................................................................................................2
Terminology............................................................................................................2
References .............................................................................................................3
New Features in the Mobile Celeron Processor.....................................................4
2.1.1 On-die GTL+ Termination .........................................................................4
2.1.2 Streaming SIMD Extensions .....................................................................4
2.1.3 Signal Differences Between the Mobile Celeron Processors in the
BGA1/Micro-PGA1 and the Mobile Celeron BGA2/Micro-PGA2 ..............4
Power Management ...............................................................................................5
2.2.1 Clock Control Architecture.........................................................................5
2.2.2 Normal State..............................................................................................5
2.2.3 Auto Halt State ..........................................................................................5
2.2.4 Stop Grant State........................................................................................6
2.2.5 Quick Start State .......................................................................................7
2.2.6 HALT/Grant Snoop State ..........................................................................7
2.2.7 Sleep State ................................................................................................7
2.2.8 Deep Sleep State ......................................................................................8
2.2.9 Operating System Implications of Low-power States ...............................8
GTL+ Signals..........................................................................................................9
Mobile Celeron Processor CPUID..........................................................................9
Processor System Signals ...................................................................................10
3.1.1 Power Sequencing Requirements...........................................................11
3.1.2 Test Access Port (TAP) Connection .......................................................11
3.1.3 Catastrophic Thermal Protection.............................................................12
3.1.4 Unused Signals .......................................................................................12
3.1.5 Signal State in Low-power States ...........................................................12
3.1.5.1
System Bus Signals ..............................................................12
3.1.5.2
CMOS and Open-drain Signals.............................................12
3.1.5.3
Other Signals.........................................................................13
Power Supply Requirements................................................................................13
3.2.1 Decoupling Recommendations ...............................................................13
3.2.2 Voltage Planes ........................................................................................13
System Bus Clock and Processor Clocking .........................................................14
Maximum Ratings.................................................................................................14
DC Specifications .................................................................................................15
AC Specifications .................................................................................................17
3.6.1 System Bus, Clock, APIC, TAP, CMOS, and Open-drain AC
Specifications ..........................................................................................17
System Bus Clock (BCLK) and PICCLK AC Signal Quality Specifications .........29
Order#-XXX
Mobile Celeron Processor Features .............................................................................................4
2.2
2.3
2.4
3.0
3.1
Electrical Specifications ..............................................................................................................10
3.2
3.3
3.4
3.5
3.6
4.0
System Signal Simulations .........................................................................................................29
4.1
Datasheet
Mobile Intel® Celeron™ Processor (0.18µ) in BGA2 and Micro-PGA2 Packages
at 700 MHz, 650 MHz, 600 MHz, 550 MHz, 500 MHz, 450 MHz,
Low-voltage 500 MHz, and Low-voltage 400A MHz
4.2
4.3
5.0
GTL+ AC Signal Quality Specifications................................................................30
Non-GTL+ Signal Quality Specifications ..............................................................33
4.3.1 PWRGOOD Signal Quality Specifications ..............................................34
Surface-mount BGA2 Package Dimensions ........................................................35
Socketable Micro-PGA2 Package Dimensions ....................................................38
Signal Listings ......................................................................................................40
Thermal Diode ......................................................................................................49
Description............................................................................................................50
7.1.1 Quick Start Enable ..................................................................................50
7.1.2 System Bus Frequency ...........................................................................50
7.1.3 APIC Enable ............................................................................................50
Clock Frequencies and Ratios .............................................................................50
Alphabetical Signal Reference .............................................................................51
Signal Summaries ................................................................................................62
Introduction..........................................................................................................64
Filter Specification ...............................................................................................64
Recommendation for Mobile Systems .................................................................65
Comments ...........................................................................................................66
Mechanical Specifications...........................................................................................................35
5.1
5.2
5.3
6.0
7.0
Thermal Specifications ................................................................................................................48
6.1
7.1
Processor Initialization and Configuration ................................................................................50
7.2
8.0
8.1
8.2
A.1
A.2
A.3
A.4
Processor Interface ......................................................................................................................51
Appendix A: PLL RLC Filter Specification..............................................................................................64
Datasheet
Order#-XXX
Mobile Intel® Celeron™ Processor (0.18µ) in BGA2 and Micro-PGA2 Packages
at 700 MHz, 650 MHz, 600 MHz, 550 MHz, 500 MHz, 450 MHz,
Low-voltage 500 MHz, and Low-voltage 400A MHz
Figures
Figure 1. Signal Groups of a Mobile Celeron Processor-Based System ............................1
Figure 2. Clock Control States ............................................................................................6
Figure 3. Vcc Ramp Rate Requirement ............................................................................11
Figure 4. PLL RLC Filter....................................................................................................13
Figure 5. PICCLK/TCK Clock Timing Waveform...............................................................23
Figure 6. BCLK Timing Waveform ....................................................................................23
Figure 7. Valid Delay Timings ...........................................................................................24
Figure 8. Setup and Hold Timings.....................................................................................24
Figure 9. Cold/Warm Reset and Configuration Timings ...................................................25
Figure 10. Power-on Reset Timings..................................................................................25
Figure 11. Test Timings (Boundary Scan) ........................................................................26
Figure 12. Test Reset Timings ..........................................................................................26
Figure 13. Quick Start/Deep Sleep Timing........................................................................27
Figure 14. Stop Grant/Sleep/Deep Sleep Timing..............................................................28
Figure 15. BCLK/PICCLK Generic Clock Waveform ........................................................30
Figure 16. Low to High, GTL+ Receiver Ringback Tolerance...........................................31
Figure 17. High to Low, GTL+ Receiver Ringback Tolerance...........................................32
Figure 18. Maximum Acceptable Overshoot/Undershoot Waveform................................33
Figure 19. Surface-mount BGA2 Package - Top and Side View ......................................36
Figure 20. Surface-mount BGA2 Package - Bottom View ................................................37
Figure 21. Socketable Micro-PGA2 Package - Top and Side View ..................................39
Figure 22. Socketable Micro-PGA2 Package - Bottom View ............................................40
Figure 23. Pin/Ball Map - Top View...................................................................................41
Figure 24. PWRGOOD Relationship at Power On............................................................58
Figure 25. PLL Filter Specifications...................................................................................65
Datasheet
Order#-XXX
京公网安备 11010802033920号
EEWORLD
