8T49N242-DDDNLGI# datasheet, PDF

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8T49N242-DDDNLGI#: DescriptionClock Generator; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，63 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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8T49N242-DDDNLGI# Overview

Clock Generator

8T49N242-DDDNLGI# Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
package instruction	VFQFN-40
Reach Compliance Code	compliant
Other features	ALSO OPERATES AT 3.3V SUPPLY NOMINAL, CLK0, CLK1 ACCEPT FREQ 8KHZ TO 875MHZ
JESD-30 code	S-XQCC-N40
length	6 mm
Number of terminals	40
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Maximum output clock frequency	1000 MHz
Package body material	UNSPECIFIED
encapsulated code	HVQCCN
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260
Master clock/crystal nominal frequency	50 MHz
Maximum seat height	1 mm
Maximum supply voltage	2.625 V
Minimum supply voltage	2.375 V
Nominal supply voltage	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	6 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER

8T49N242-DDDNLGI# Preview

FemtoClock

NG Universal Frequency

Translator

8T49N242

Datasheet

General Description

The 8T49N242 has one fractional-feedback PLL that can be used as

a jitter attenuator and frequency translator. It is equipped with four

integer output dividers, allowing the generation of up to four different

output frequencies, ranging from 8kHz to 1GHz. These frequencies

are completely independent of the input reference frequencies and

the crystal reference frequency. The device places virtually no

constraints on input to output frequency conversion, supporting all

FEC rates, including the new revision of ITU-T Recommendation

G.709 (2009), most with 0ppm conversion error. The outputs may

select among LVPECL, LVDS, HCSL or LVCMOS output levels.

This makes it ideal to be used in any frequency synthesis application,

including 1G, 10G, 40G and 100G Synchronous Ethernet, OTN, and

SONET/SDH, including ITU-T G.709 (2009) FEC rates.

The 8T49N242 accepts up to two differential or single-ended input

clocks and a fundamental-mode crystal input. The internal PLL can

lock to either of the input reference clocks or just to the crystal to

behave as a frequency synthesizer. The PLL can use the second

input for redundant backup of the primary input reference, but in this

case, both input clock references must be related in frequency.

The device supports hitless reference switching between input

clocks. The device monitors both input clocks for Loss of Signal

(LOS), and generates an alarm when an input clock failure is

detected. Automatic and manual hitless reference switching options

are supported. LOS behavior can be set to support gapped or

un-gapped clocks.

The 8T49N242 supports holdover. The holdover has an initial

accuracy of ±50ppB from the point where the loss of all applicable

input reference(s) has been detected. It maintains a historical

average operating point for the PLL that may be returned to in

holdover at a limited phase slope.

The PLL has a register-selectable loop bandwidth from 0.2Hz to

6.4kHz.

The device supports Output Enable & Clock Select inputs and Lock,

Holdover & LOS status outputs.

The device is programmable through an I

C interface. It also

supports I

C master capability to allow the register configuration to

be read from an external EEPROM.

Programming with IDT’s

Timing Commander

software is

recommended for optimal device performance. Factory

pre-programmed devices are also available.

Applications

• OTN or SONET / SDH equipment

• Gigabit and Terabit IP switches / routers including Synchronous

Ethernet

• Video broadcast

Features

• Supports SDH/SONET and Synchronous Ethernet clocks including

all FEC rate conversions

• 0.35ps RMS Typical Jitter (including spurs): 12kHz to 20MHz

• Operating Modes: Synthesizer, Jitter Attenuator

• Operates from a 10MHz to 50MHz fundamental-mode crystal or a

10MHz to 125MHz external oscillator

• Initial holdover accuracy of +50ppb.

• Accepts up to 2 LVPECL, LVDS, LVHSTL or LVCMOS input clocks

• Accepts frequencies ranging from 8kHz to 875MHz

• Auto and manual clock selection with hitless switching

• Clock input monitoring including support for gapped clocks

• Phase-slope limiting and fully hitless switching options to control

output clock phase transients

• Generates four LVPECL / LVDS / HCSL or eight LVCMOS output

clocks

• Output frequencies ranging from 8kHz up to 1.0GHz

(differential)

• Output frequencies ranging from 8kHz to 250MHz (LVCMOS)

• Integer divider ranging from ÷4 to ÷786,420 for each output

• Programmable loop bandwidth settings from 0.2Hz to 6.4kHz

• Optional fast-lock function

• Four General Purpose I/O pins with optional support for status &

control:

• Two Output Enable control inputs provide control over the four

clocks

• Manual clock selection control input

• Lock, Holdover and Loss-of-Signal alarm outputs

• Open-drain Interrupt pin

• Register programmable through I

C or via external I

C EEPROM

• Full 2.5V or 3.3V supply modes, 1.8V support for LVCMOS outputs,

GPIO and control pins

• -40°C to 85°C ambient operating temperature

• Package: 40QFN, lead-free (RoHS 6)

REVISION 6, November 1, 2016

8T49N242 Datasheet

8T49N242 Block Diagram

CLK0

CLK1

Input Clock

Monitoring,

Priority,

Selection

IntN Divider

FracN

Feedback

PLL

IntN Divider

XTAL

OSC

IntN Divider

Reset

Logic

IntN Divider

OTP

C Slave

Status &

Control

Registers

GPIO

Logic

nRST

C Master

SCLK

SDATA

Serial EEPROM

nWP

S_A[1:0]

GPIO

nINT

Figure 1. 8T49N242 Functional Block Diagram

Revision 6, November 1, 2016

8T49N242 Datasheet

Pin Assignment

GPIO[3]

GPIO[2]

CCO3

30 29 28 27 26 25 24 23 22 21

CCO2

nINT

CCA

nQ3

nQ2

nRST

CCA

OSCI

OSCO

nWP

CCCS

CAP

CAP_REF

CCA

S_A0

S_A1

nCLK1

CLK1

nCLK0

CLK0

SCLK

SDATA

8T49N242

GPIO[0]

GPIO[1]

CCA

nQ0

CCO0

nQ1

40-pin 6mm x 6mm VFQFPN

Figure 2. 8T49N242 Pinout Drawing

CCO1

Revision 6, November 1, 2016

8T49N242 Datasheet

Pin Description and Pin Characteristic Tables

Table 1. Pin Descriptions

Number

Name

CCA

GPIO[0]

CCO0

nQ0

GPIO[1]

nQ1

CCO1

SDATA

SCLK

CLK0

nCLK0

CLK1

nCLK1

S_A1

CCO2

nQ2

GPIO[2]

nQ3

CCO3

GPIO[3]

nINT

CCA

Power

I/O

Power

I/O

Power

I/O

Power

I/O

Power

I/O

Power

Pullup

Universal

Pullup

Universal

Pulldown

Pullup /

Pulldown

Pullup /

Pulldown

Pullup

Universal

Pullup

Universal

Pullup

Type

Description

Analog function supply for core analog functions. 2.5V or 3.3V supported.

Analog function supply for analog functions associated with the PLL. 2.5V or

3.3V supported.

General-purpose input-output. LVTTL / LVCMOS Input levels.

High-speed output supply for output pair Q0, nQ0. 2.5V or 3.3V supported for

differential output types. LVCMOS outputs also support 1.8V.

Output Clock 0. Please refer to the

Section, “Output Drivers”

for more details.

Output Clock 0. Please refer to the

Section, “Output Drivers”

for more details.

General-purpose input-output. LVTTL / LVCMOS Input levels.

Output Clock 1. Please refer to the

Section, “Output Drivers”

for more details.

Output Clock 1. Please refer to the

Section, “Output Drivers”

for more details.

High-speed output supply for output pair Q1, nQ1. 2.5V or 3.3V supported for

differential output types. LVCMOS outputs also support 1.8V.

C interface bi-directional data.

C interface bi-directional clock.

Core digital function supply. 2.5V or 3.3V supported.

Negative supply voltage. All V

pins and EPAD must be connected before any

positive supply voltage is applied.

Core digital function supply. 2.5V or 3.3V supported.

Non-inverting differential clock input 0.

Inverting differential clock input 0.

/ 2 when left floating (set by internal pullup / pulldown resistors)

Non-inverting differential clock input 1.

Inverting differential clock input 1.

/ 2 when left floating (set by internal pullup / pulldown resistors).

C Address Bit A1

High-speed output supply voltage for output pair Q2, nQ2. 2.5V or 3.3V

supported for differential output types. LVCMOS outputs also support 1.8V.

Output Clock 2. Please refer to the

Section, “Output Drivers”

for more details.

Output Clock 2. Please refer to the

Section, “Output Drivers”

for more details.

General-purpose input-output. LVTTL / LVCMOS Input levels.

Output Clock 3. Please refer to the

Section, “Output Drivers”

for more details.

Output Clock 3. Please refer to the

Section, “Output Drivers”

for more details.

High-speed output supply voltage for output pair Q3, nQ3. 2.5V or 3.3V

supported for differential output types. LVCMOS outputs also support 1.8V.

General-purpose input-output. LVTTL / LVCMOS Input levels.

Open-drain

Interrupt output.

with pullup

Analog function supply for analog functions associated with PLL. 2.5V or 3.3V

supported.

Pullup

Master Reset input. LVTTL / LVCMOS interface levels:

0 = All registers and state machines are reset to their default values

1 = Device runs normally

nRST

Revision 6, November 1, 2016

8T49N242 Datasheet

Number

Name

CCA

OSCI

Power

Type

Description

Analog function supply for core analog functions. 2.5V or 3.3V supported.

Crystal Input. Accepts a 10MHz – 50MHz reference from a clock oscillator or a

12pF fundamental mode, parallel-resonant crystal. For proper device

functionality, a crystal or external oscillator must be connected to this pin.

Crystal Output. This pin must be connected to a crystal. If an oscillator is

connected to OSCI, then this pin must be left unconnected.

Pullup

Write Protect input. LVTTL / LVCMOS interface levels.

0 = Write operations on the serial port will complete normally, but will have no

effect except on interrupt registers.

Output supply for Control & Status pins:

GPIO[3:0], SDATA, SCLK, S_A1, S_A0, nINT, nWP, nRST

1.8V, 2.5V or 3.3V supported

PLL External Capacitance. A 0.1µF capacitance value across CAP and

CAP_REF pins is recommended.

PLL External Capacitance. A 0.1µF capacitance value across CAP and

CAP_REF pins is recommended.

Analog function supply for analog functions associated with PLL. 2.5V or 3.3V

supported.

OSCO

nWP

CCCS

Power

ePAD

CAP

CAP_REF

CCA

S_A0

Exposed Pad

Analog

Power

Pulldown

C Address Bit A0.

Negative supply voltage. All V

pins and ePAD must be connected before any

positive supply voltage is applied.

NOTE 1:

Pullup

and

Pulldown

refer to internal input resistors. See

Table 2,

Pin Characteristics,

for typical values.

Table 2. Pin Characteristics,

= V

CCOX

= 3.3V±5% or 2.5V±5%

Symbol

PULLUP

Parameter

Input Capacitance

Input Pullup

Resistor

Input Pulldown

Resistor

GPIO[3:0],

nRST, nWP,

SDATA, SCLK

S_A0, S_A1

LVCMOS

Power Dissipation

Capacitance

(per output pair)

LVCMOS

LVDS, HCSL or

LVPECL

GPIO[3:0]

OUT

Output

Impedance

LVCMOS

Q[3:0], nQ[3:0]

NOTE 1: V

CCOX

denotes: V

CCO0,

CCO1,

CCO2

or V

CCO3.

NOTE 2: This specification does not apply to the OSCI or OSCO pins.

CCOX

= 3.465V

CCOX

= 2.625V

CCOX

= 1.89V

CCOX

= 3.465V or 2.625V

CCCS

= 3.3V

CCCS

= 2.5V

CCCS

= 1.8V

CCOX

= 3.3V

CCOX

= 2.5V

CCOX

= 1.8V

Test Conditions

Minimum

Typical

3.5

Maximum

Units

k

PULLDOWN

11.5

10.5

2.5

k



Revision 6, November 1, 2016

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8T49N242-DDDNLGI# Related Products

	8T49N242-DDDNLGI#	8T49N242-DDDNLGI
Description	Clock Generator	Clock Generator, 1000MHz, CMOS, 6 X 6 MM, ROHS COMPLIANT, MO-220VJJC-3, VFQFN-40
Is it Rohs certified?	conform to	conform to
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
package instruction	VFQFN-40	VFQFN-40
Reach Compliance Code	compliant	compliant
Other features	ALSO OPERATES AT 3.3V SUPPLY NOMINAL, CLK0, CLK1 ACCEPT FREQ 8KHZ TO 875MHZ	IT ALSO OPERATES AT 3.3V NOMINAL SUPPLY
JESD-30 code	S-XQCC-N40	S-XQCC-N40
length	6 mm	6 mm
Number of terminals	40	40
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Maximum output clock frequency	1000 MHz	1000 MHz
Package body material	UNSPECIFIED	UNSPECIFIED
encapsulated code	HVQCCN	HVQCCN
Package shape	SQUARE	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260	260
Master clock/crystal nominal frequency	50 MHz	50 MHz
Maximum seat height	1 mm	1 mm
Maximum supply voltage	2.625 V	2.625 V
Minimum supply voltage	2.375 V	2.375 V
Nominal supply voltage	2.5 V	2.5 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal form	NO LEAD	NO LEAD
Terminal pitch	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD
Maximum time at peak reflow temperature	30	30
width	6 mm	6 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER

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