OBSOLETE
256K, 512K x 64
SGRAM SODIMMs
SYNCHRONOUS
GRAPHICS RAM SODIMM
FEATURES
• JEDEC pinout in a 144-pin, small-outline, dual in-line
memory module (SODIMM)
• 2MB (256K x 64) and 4MB (512K x 64)
• Fully synchronous; all signals registered on positive
edge of system clock
• Single +3.3V
±0.3V
power supply
• LVTTL-compatible inputs and outputs
• Internal pipelined operation; column address can be
changed every clock cycle
• Programmable burst lengths: 1, 2, 4, 8 or full page
• Block Write and Write-Per-Bit Modes
• Independent byte operation via DQM0-DQM7
• Auto Precharge and Auto Refresh Modes
• 17ms, 1,024-cycle refresh
• Optional serial presence-detect (SPD)
MT2LG25664(K)H, MT4LG51264(K)H
For the latest full-length data sheet, please refer to the
Micron Web site:
www.micron.com/mti/msp/html/
datasheet.html
PIN ASSIGNMENT (Front View)
144-Pin Small-Outline DIMM
(I-7; 2MB)
(I-6; 4MB)
OPTIONS
• Frequency
125 MHz
100 MHz
83 MHz
• SPD
With SPD
Without SPD
• Package
144-pin SODIMM (gold)
MARKING
-25
-10
-83
None
K
G
SGRAM COMPONENT KEY TIMING
PARAMETERS
MODULE
MARKING
-25
-10
-83
SPEED
GRADE
7ns
8ns
10ns
ACCESS
TIME
6ns
6.5ns
9ns
SETUP
TIME
2ns
2.5ns
3ns
HOLD
TIME
1ns
1ns
1ns
PART NUMBERS
PART NUMBER
MT2LG25664HG-xx
MT2LG25664KHG-xx
MT4LG51264HG-xx
MT4LG51264KHG-xx
xx = frequency
256K, 512K x 64 SGRAM SODIMMs
GM01.p65 – Rev. 2/99
CONFIGURATION
256K x 64
256K x 64
512K x 64
512K x 64
OPTIONS
SPD
SPD
PIN
FRONT
PIN
BACK
PIN
FRONT
PIN
BACK
1
V
SS
2
V
SS
73 NC/CLK1* 74
CLK0
3
DQ63
4
DQ62
75
V
DD
76
V
DD
5
DQ61
6
DQ60
77
RSVD
78
RSVD
7
DQ59
8
DQ58
79
NC (A11)
80
NC (A10)
9
DQ57
10
DQ56
81
BA0 (A9)
82
A8
11
V
DD
12
V
DD
83
A7
84
A6
13
DQ55
14
DQ54
85
V
SS
86
V
SS
15
DQ53
16
DQ52
87
A5
88
A4
17
DQ51
18
DQ50
89
A3
90
A2
19
DQ49
20
DQ48
91
A1
92
A0
21
V
SS
22
V
SS
93
V
DD
94
V
DD
23
DQMB7
24
DQMB6
95
DQ31
96
DQ30
25
DQMB5
26
DQMB4
97
DQ29
98
DQ28
27
V
DD
28
V
DD
99
DQ27
100
DQ26
29
DQ47
30
DQ46
101
DQ25
102
DQ24
31
DQ45
32
DQ44
103
V
SS
104
V
SS
33
DQ43
34
DQ42
105
DQ23
106
DQ22
35
DQ41
36
DQ40
107
DQ21
108
DQ20
37
V
SS
38
V
SS
109
DQ19
110
DQ18
39
DQ39
40
DQ38
111
DQ17
112
DQ16
41
DQ37
42
DQ36
113
V
DD
114
V
DD
43
DQ35
44
DQ34
115
DQMB3
116
DQMB2
45
DQ33
46
DQ32
117
DQMB1
118
DQMB0
47
V
DD
48
V
DD
119
V
SS
120
V
SS
49
RSVD
50
RSVD
121
DQ15
122
DQ14
51
RSVD
52
RSVD
123
DQ13
124
DQ12
53
RSVD
54
RSVD
125
DQ11
126
DQ10
55
V
SS
56
V
SS
127
DQ9
128
DQ8
57
DSF
58
RFU
129
V
DD
130
V
DD
59
RFU
60
RFU
131
DQ7
132
DQ6
61
RFU
62 SA0/NC** 133
DQ5
134
DQ4
63
V
DD
64
V
DD
135
DQ3
136
DQ2
65 NC/CS1#* 66
CS0#
137
DQ1
138
DQ0
67
RAS#
68
CAS#
139
V
SS
140
V
SS
69
WE#
70
CKE
141 SDA/NC** 142 SCL/NC**
71
V
SS
72
V
SS
143
V
DD
144
V
DD
* 4MB version only
** K version only
NOTE:
Pin symbols in parentheses are not used on these modules but may be
used for other modules in this product family. They are for reference only.
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999,
Micron Technology, Inc.
Micron is a registered trademark of Micron Technology, Inc.
OBSOLETE
256K, 512K x 64
SGRAM SODIMMs
GENERAL DESCRIPTION
The MT2LG25664(K)H and MT4LG51264(K)H SGRAM
modules are high-speed CMOS, dynamic random-access
2MB and 4MB memories organized in a small-outline, x64
configuration.
Read and write accesses to the modules are burst ori-
ented; accesses start at a selected location and continue for
a programmed number of locations in a programmed se-
quence. Accesses begin with the registration of an ACTIVE
command, which is then followed by a READ or WRITE
command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be
accessed (BA selects the bank, A0-A8 select the row). Then
the address bits registered coincident with the READ or
WRITE command are used to select the starting column
location for the burst access.
These modules provide for programmable READ or
WRITE burst lengths of 1, 2, 4 or 8 locations, or the full page,
with a burst terminate option. An AUTO PRECHARGE
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst sequence.
The modules use an internal pipelined architecture to
achieve high-speed operation. This architecture is compat-
ible with the 2n rule of prefetch architectures, but it also
allows the column address to be changed on every clock
cycle to achieve a high-speed, fully random access.
Precharging one bank while accessing the alternate bank
will hide the PRECHARGE cycles and provide seamless,
high-speed, random-access operation.
Synchronous graphics RAMs (SGRAMs) differ from syn-
chronous DRAMs (SDRAMs) by providing an eight-
column BLOCK WRITE function and a MASKED WRITE
(or WRITE-PER-BIT) function to accommodate high-
performance graphics applications. The BLOCK WRITE
and MASKED WRITE functions may be combined with
individual byte enables (DQ mask or DQM pins).
The CMOS dynamic memory structure of these
modules is designed to operate in 3.3V, low-power memory
systems. An auto refresh mode is provided, along with a
power-saving, power-down mode. All inputs and outputs
are LVTTL-compatible. (Refer to the MT41LC256K32D4
SGRAM data sheet for additional information on SGRAM
functionality.)
RESISTOR STRAPPING DETECTION
Three resistor straps are used to indicate the module
frequency and timing. Table 1 shows the settings. A logic
LOW (i.e., 0) indicates that the strapping resistor is tied to
ground (V
SS
). A logic HIGH (i.e., 1) indicates that the
strapping resistor is tied to V
DD
.
Table 1
MODULE FREQUENCY
125 MHz
100 MHz
83 MHz
DQ31
0
0
0
DQ30
1
1
0
DQ29
1
0
1
SERIAL PRESENCE-DETECT OPERATION
These modules can also incorporate serial presence-
detect (SPD). The SPD function is implemented using a
2,048-bit EEPROM. This nonvolatile storage device con-
tains 256 bytes. The first 128 bytes can be programmed by
Micron to identify the module type and various DRAM
organizations and timing parameters. The remaining 128
bytes of storage are available for use by the customer.
System READ/WRITE operations between the master (sys-
tem logic) and the slave EEPROM device (DIMM) occur via
a standard IIC bus using the DIMM’s SCL (clock) and SDA
(data) signals, together with SA(0), which provide two
unique DIMM/EEPROM addresses.
256K, 512K x 64 SGRAM SODIMMs
GM01.p65 – Rev. 2/99
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999,
Micron Technology, Inc.
OBSOLETE
256K, 512K x 64
SGRAM SODIMMs
FUNCTIONAL BLOCK DIAGRAM
MT2LG25664(K)H (2MB)
DQ0-DQ31
DQMB0-DQMB3
DQ32-DQ63
DQMB4-DQMB7
36
DQ0-DQ31
DQM0-DQM3
U0
CAS#
RAS#
WE#
CS0#
CLK0
BA0
CAS#
RAS#
WE#
CS#
CLK
BA
A0–A8
CAS#
RAS#
WE#
CS#
CLK
BA
36
DQ0-DQ31
DQM0-DQM3
U1
CKE
DSF
CKE
DSF
CKE
DSF
A0–A8
9
9
A0-A8
SPD
SCL
A0 A1 A2
SA0
SDA
U0-U1 = MT41LC256K32D4
V
DD
V
SS
U0-U1
U0-U1
256K, 512K x 64 SGRAM SODIMMs
GM01.p65 – Rev. 2/99
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999,
Micron Technology, Inc.
OBSOLETE
256K, 512K x 64
SGRAM SODIMMs
FUNCTIONAL BLOCK DIAGRAM
MT4LG51264(K)H (4MB)
DQ0-DQ31
DQMB0-DQMB3
DQ32-DQ63
DQMB4-DQMB7
36
DQ0-DQ31
DQM0-DQM3
U0
CAS#
RAS#
WE#
CS0#
CLK0
BA0
CAS#
RAS#
WE#
CS#
CLK
BA
A0–A8
CAS#
RAS#
WE#
CS#
CLK
BA
36
DQ0-DQ31
DQM0-DQM3
U1
CKE
DSF
CKE
DSF
CKE
DSF
A0–A8
9
.
.
.
DQ0-DQ31
DQMB0-DQMB3
9
A0-A8
DQ32-DQ63
DQMB4-DQMB7
36
CKE DQ0-DQ31
DQM0-DQM3
DSF
U2
CAS#
RAS#
WE#
CS1#
CLK1
CS#
CLK
BA
A0–A8
CAS#
RAS#
WE#
CS#
CLK
BA
36
CKE DQ0-DQ31
DQM0-DQM3
DSF
U3
A0–A8
9
9
SPD
SCL
A0 A1 A2
SA0
SDA
U0-U3 = MT41LC256K32D4
V
DD
V
SS
U0-U3
U0-U3
NOTE:
All resistor values are 10 ohms unless otherwise specified.
256K, 512K x 64 SGRAM SODIMMs
GM01.p65 – Rev. 2/99
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999,
Micron Technology, Inc.
OBSOLETE
256K, 512K x 64
SGRAM SODIMMs
PIN DESCRIPTIONS
PIN NUMBERS
74, 73
SYMBOL
CLK0, CLK1
TYPE
Input
DESCRIPTION
Clock: CLK is driven by the system clock. All SGRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal
burst counter and controls the output registers.
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK
signal. After both banks are precharged, deactivating the clock provides
power-down mode and self refresh mode. CKE is synchronous except after
the device enters power-down and self refresh modes, where CKE
becomes asynchronous until after exiting the same mode. The input
buffers, including CLK, are disabled during power-down and self refresh
modes, providing low standby power. CKE may be tied HIGH.
Chip Select: CS# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when CS# is
registered HIGH. CS# provides for external bank selection on systems with
multiple banks. CS# is considered part of the command code.
Command Inputs: RAS#, WE#, CAS# and DSF define the command being
entered.
Input/Output Mask: DQMB0-DQMB3 are byte-specific, nonpersistent I/O
buffer controls. The I/O buffers are placed in a High-Z state when DQMB is
sampled HIGH. Input data is masked when DQMB is sampled HIGH during
a WRITE cycle. Output data is masked (two-clock latency) when DQMB is
sampled HIGH during a READ cycle. DQMB0 masks DQ0-DQ7, DQMB1
masks DQ8-DQ15, DQMB2 masks DQ16-DQ23, and DQMB3 masks
DQ24-DQ31. This pattern repeats for the remaining DQMBs.
Bank Address: BA0 defines to which bank the ACTIVE, READ, WRITE or
PRECHARGE command is being applied. BA0 is also used to program the
tenth bit of the Mode and Special Mode Registers.
Address Inputs: A0-A8 are sampled during the ACTIVE command (row-
address A0-A8) and READ/WRITE command (column-address A0-A7, with
A8 defining AUTO PRECHARGE) to select one location out of the memory
array available in the respective bank. A8 is sampled during a
PRECHARGE command to determine if both banks are to be precharged
(A8 HIGH). The address inputs also provide the op-code during a LOAD
MODE REGISTER or LOAD SPECIAL MODE REGISTER command.
Data I/O: Data bus. The I/Os are byte-maskable during READs and
WRITEs.The DQs also serve as column/byte mask inputs during BLOCK
WRITEs.
Serial Presence-Detect Data. SDA is a bidirectional pin used to transfer
addresses and data into and out of the presence-detect portion of the
module.
Serial Clock for Presence-Detect. SCL is used to synchronize the
presence-detect data transfer to and from the module.
Presence-Detect Address Input. This pin is used to configure the
presence-detect device.
70
CKE
Input
66, 65
CS0#, CS1#
Input
67-69, 57
23-26, 115-118
RAS#, CAS#
WE#, DSF
DQMB0-
DQMB7
Input
Input
81
BA0
Input
82-84, 87-92
A0-A8
Input
3-10, 13-20,
29-36, 39-46,
95-102, 105-112,
121-128, 131-138
141
DQ0-DQ63
Input/
Output
SDA
Input/
Output
Input
Input
142
62
SCL
SA0
256K, 512K x 64 SGRAM SODIMMs
GM01.p65 – Rev. 2/99
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999,
Micron Technology, Inc.
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