K7A403601B
K7A403201B
Document Title
128Kx36/x32 Synchronous SRAM
128Kx36 & 128Kx32-Bit Synchronous Pipelined Burst SRAM
Revision History
Rev. No.
0.0
0.1
History
1. Initial draft
1. Changed DC parameters
Icc ; from 350mA to 290mA at -16,
from 330mA to 270mA at -15,
from 300mA to 250mA at -14,
I
SB1
; from 100mA to 80mA
1 Delete Pass-Through
1. Add x32 org and industrial temperature
1. Final spec release
2. Changed Pin Capacitance
- Cin ; from 5pF to 4pF
- Cout ; from 7pF to 6pF
Draft Date
May. 15. 2001
June. 12. 2001
Remark
Preliminary
Preliminary
0.2
0.3
1.0
June. 25. 2001
Aug. 11. 2001
Nov. 15. 2001
Preliminary
Preliminary
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Nov 2001
Rev 1.0
K7A403601B
K7A403201B
128Kx36/x32 Synchronous SRAM
4Mb SB/SPB Synchronous SRAM Ordering Information
Org.
Part Number
Mode
VDD
Speed
FT ; Access Time(ns)
Pipelined ; Cycle Time(MHz)
6.5/7.5/8.0 ns
167/138 MHz
300/275/250/225/200 MHz
6.5/7.5/8.0 ns
167/138 MHz
300/275/250/225/200 MHz
167/138/ MHz
6.5/7.5/8.0 ns
167/138 MHz
300/275/250/225/200 MHz
167/138 MHz
Q
(100TQFP)
C
(Commercial
Temperature
Range)
I:
(Industrial
Temperature
Range)
PKG
Temp
K7B401825B-QC(I)65/75/80
256Kx18 K7A401800B-QC(I)16/14
K7A401809B-QC(I)30/27/25/22/20
K7B403225B-QC(I)65/75/80
128Kx32
K7A403200B-QC(I)16/14
K7A403209B-QC(I)30/27/25/22/20
K7A403201B-QC(I)16/14
K7B403625B-QC(I)65/75/80
128Kx36
K7A403600B-QC(I)16/14
K7A403609B-QC(I)30/27/25/22/20
K7A403601B-QC(I)16/14
SB
SPB(2E1D)
SPB(2E1D)
SB
SPB(2E1D)
SPB(2E1D)
SPB(2E2D)
SB
SPB(2E1D)
SPB(2E1D)
SPB(2E2D)
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
-2-
Nov 2001
Rev 1.0
K7A403601B
K7A403201B
128Kx36/x32 Synchronous SRAM
128Kx36 & 128Kx32-Bit Synchronous Pipelined Burst SRAM
FEATURES
• Synchronous Operation.
• 2 Stage Pipelined operation with 4 Burst.
• On-Chip Address Counter.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• V
DD
= 3.3V+0.3V/-0.165V Power Supply.
• V
DDQ
Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O
• 5V Tolerant Inputs Except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a
linear burst.
• Three Chip Enables for simple depth expansion with No Data
Contention ; 2cycle Enable, 2cycle Disable.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
• 100-TQFP-1420A
• Operating in commeical and industrial temperature range.
GENERAL DESCRIPTION
The K7A403601B and K7A403201B are a 4,718,592-bit
Synchronous Static Random Access Memory designed for
high performance second level cache of Pentium and Power
PC based System.
It is organized as 128K words of 36bits and integrates
address and control registers, a 2-bit burst address counter
and added some new functions for high performance cache
RAM applications; GW, BW, LBO, ZZ. Write cycles are inter-
nally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is
performed by the combination of WEx and BW when GW is
high. And with CS
1
high, ADSP is blocked to control signals.
Burst cycle can be initiated with either the address status
processor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated internally
in the system′s burst sequence and are controlled by the
burst address advance(ADV) input.
LBO pin is DC operated and determines burst sequence(lin-
ear or interleaved).
ZZ pin controls Power Down State and reduces Stand-by
current regardless of CLK.
The K7A403601B and K7A403201B are fabricated using
SAMSUNG′s high performance CMOS technology and is
available in a 100pin TQFP package. Multiple power and
ground pins are utilized to minimize ground bounce.
FAST ACCESS TIMES
PARAMETER
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol
t
CYC
t
CD
t
OE
-16 -14 Unit
6.0
3.5
3.5
7.2
4.0
4.0
ns
ns
ns
LOGIC BLOCK DIAGRAM
CLK
LBO
ADV
ADSC
BURST CONTROL
LOGIC
BURST
ADDRESS
COUNTER
A′
0
~A′
1
CONTROL
REGISTER
128Kx36/32
MEMORY
ARRAY
A
0
~A
1
ADDRESS
REGISTER
A
2
~A
16
ADSP
A
0
~A
16
CS
1
CS
2
CS
2
GW
BW
DATA-IN
REGISTER
CONTROL
REGISTER
WEa
WEb
WEc
WEd
OE
ZZ
DQa
0
~ DQd
7
DQPa ~ DQPd
CONTROL
LOGIC
OUTPUT
REGISTER
BUFFER
-3-
Nov 2001
Rev 1.0
K7A403601B
K7A403201B
PIN CONFIGURATION
(TOP VIEW)
128Kx36/x32 Synchronous SRAM
ADSC
ADSP
WEd
WEb
WEa
WEc
ADV
83
CLK
CS
1
CS
2
CS
2
V
DD
GW
V
SS
BW
OE
A
6
A
7
A
8
82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
81
A
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
N.C.
N.C.
N.C.
N.C.
V
DD
A
5
A
4
A
3
A
2
A
1
A
0
A
10
A
11
A
12
A
13
A
14
A
15
PIN NAME
SYMBOL
A
0
- A
16
PIN NAME
Address Inputs
TQFP PIN NO.
32,33,34,35,36,37,
44,45,46,47,48,49,
50,81,82,99,100
83
84
85
89
98
97
92
93,94,95,96
86
88
87
64
31
SYMBOL
V
DD
V
SS
N.C.
DQa
0
~a
7
DQb
0
~b
7
DQc
0
~c
7
DQd
0
~d
7
DQPa~P
d
/NC
V
DDQ
V
SSQ
PIN NAME
Power Supply(+3.3V)
Ground
No Connect
Data Inputs/Outputs
TQFP PIN NO.
15,41,65,91
17,40,67,90
14,16,38,39,42,43,66
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
ADV
ADSP
ADSC
CLK
CS
1
CS
2
CS
2
WEx
OE
GW
BW
ZZ
LBO
Burst Address Advance
Address Status Processor
Address Status Controller
Clock
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
LBO
V
SS
Output Power Supply
(2.5V or 3.3V)
Output Ground
A
16
50
DQPc/NC
DQc
0
DQc
1
V
DDQ
V
SSQ
DQc
2
DQc
3
DQc
4
DQc
5
V
SSQ
V
DDQ
DQc
6
DQc
7
N.C.
V
DD
N.C.
V
SS
DQd
0
DQd
1
V
DDQ
V
SSQ
DQd
2
DQd
3
DQd
4
DQd
5
V
SSQ
V
DDQ
DQd
6
DQd
7
DQPd/NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
K7A403601B(128Kx36)
K7A403201B(128Kx32)
DQPb/NC
DQb
7
DQb
6
V
DDQ
V
SSQ
DQb
5
DQb
4
DQb
3
DQb
2
V
SSQ
V
DDQ
DQb
1
DQb
0
V
SS
N.C.
V
DD
ZZ
DQa
7
DQa
6
V
DDQ
V
SSQ
DQa
5
DQa
4
DQa
3
DQa
2
V
SSQ
V
DDQ
DQa
1
DQa
0
DQPa/NC
-4-
Nov 2001
Rev 1.0
K7A403601B
K7A403201B
FUNCTION DESCRIPTION
128Kx36/x32 Synchronous SRAM
The K7A4036/3201B are synchronous SRAM designed to support the burst address accessing sequence of the P6 and Power PC
based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The start and duration
of the burst access is controlled by ADSC, ADSP and ADV and chip select pins.
The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with
ADV.
When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ
returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally.
Read cycles are initiated with ADSP(regardless of WEx and ADSC)using the new external address clocked into the on-chip address
register whenever ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with OE. In read oper-
ation the data of cell array accessed by the current address, registered in the Data-out registers by the positive edge of CLK, are car-
ried to the Data-out buffer by the next positive edge of CLK. The data, registered in the Data-out buffer, are projected to the output
pins. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on the subsequent clock edges. The address
increases internally for the next access of the burst when WEx are sampled High and ADV is sampled low. And ADSP is blocked to
control signals by disabling CS
1
.
All byte write is done by GW(regaedless of BW and WEx.), and each byte write is performed by the combination of BW and WEx
when GW is high.
Write cycles are performed by disabling the output buffers with OE and asserting WEx. WEx are ignored on the clock edge that sam-
ples ADSP low, but are sampled on the subsequent clock edges. The output buffers are disabled when WEx are sampled
Low(regaedless of OE). Data is clocked into the data input register when WEx sampled Low. The address increases internally to the
next address of burst, if both WEx and ADV are sampled Low. Individual byte write cycles are performed by any one or more byte
write enable signals(WEa, WEb, WEc or WEd) sampled low. The WEa control DQa
0
~ DQa
7
and DQPa, WEb controls DQb
0
~ DQb
7
and DQPb, WEc controls DQc
0
~ DQc
7
and DQPc, and WEd control DQd
0
~ DQd
7
and DQPd. Read or write cycle may also be initi-
ated with ADSC, instead of ADSP. The differences between cycles initiated with ADSC and ADSP as are follows;
ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
WEx are sampled on the same clock edge that sampled ADSC low(and ADSP high).
Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external
address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state
of the LBO pin. When this pin is Low, linear burst sequence is selected. When this pin is High, Interleaved burst sequence is
selected.
BURST SEQUENCE TABLE
LBO PIN
HIGH
First Address
Case 1
A
1
0
0
1
1
A
0
0
1
0
1
A
1
0
0
1
1
Case 2
A
0
1
0
1
0
A
1
1
1
0
0
Case 3
A
0
0
1
0
1
(Interleaved Burst)
Case 4
A
1
1
1
0
0
A
0
1
0
1
0
Fourth Address
BURST SEQUEN LE
LBO PIN
LOW
First Address
Case 1
A
1
0
0
1
1
A
0
0
1
0
1
A
1
0
1
1
0
Case 2
A
0
1
0
1
0
A
1
1
1
0
0
Case 3
A
0
0
1
0
1
A
1
1
0
0
1
(Linear Burst)
Case 4
A
0
1
0
1
0
Fourth Address
Note :
1. LBO pin must be tied to High or Low, and Floating State must not be allowed
.
-5-
Nov 2001
Rev 1.0
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