K3P7P(Q)1000B-FC
64M-Bit (8Mx8 /4Mx16) CMOS MASK ROM
FEATURES
•
Switchable organization
8,388,608 x 8(byte mode)
4,194,304 x 16(word mode)
•
Fast access Time (C
L
=30pF)
Random Access Time/Page Access Time : 100/30ns(max.)
•
Supply voltage
V
CC
: single +3.3V/ single +3.0V
V
CCQ
: single +1.8V
•
8 words/16 bytes page access
•
Temperature : 0°C ~ +70°C
•
Current consumption
Operating(I
CC
) : 60mA (max)
Standby(I
SB2
) : 50uA (max)
•
Fully static operation
•
All inputs and outputs TTL compatible
•
Package
K3P7P(Q)1000B-FC : 48-CSP with 0.75mm ball pitch
Preliminary Information
CMOS MASK ROM
GENERAL DESCRIPTION
The K3P7P(Q)1000B-FC is a fully static mask programmable
ROM fabricated using silicon gate CMOS process technology,
and is organized either as 8,388,608 x 8 bit(byte mode) or as
4,194,304 x 16 bit(word mode) depending on BHE voltage level.
This device includes page read mode function, page read mode
allows 8 words (or 16 bytes) of data to be read fast in the same
page, CE and A
3
~ A
21
should not be changed.
This device operates with 3.0V or 3.3V power supply, and all
inputs and outputs are TTL compatible.
Because of its asynchronous operation, it requires no external
clock assuring extremely easy operation.
It is suitable for use in program memory of microprocessor, and
operating system and/or application software storage for hand-
held application.
The K3P7P(Q)1000B-FC is packaged in a 48-CSP with 0.75mm
ball pitch and 6x8 ball array.
FUNCTIONAL BLOCK DIAGRAM
Pin Name
A
21
X
MEMORY CELL
MATRIX
(4,194,304x16/
8,388,608x8)
A
0
- A
2
A
3
- A
21
Q
0
- Q
14
Q
15
/A
-1
BHE
Y
BUFFERS
AND
A
3
A
0~
A
2
A
-1
DECODER
DATA OUT
BUFFERS
CE
SENSE AMP.
OE
V
CC
V
CCQ
V
SS
NC
Pin Function
Page Address Inputs
Address Inputs
Data Outputs
Output 15(Word mode)/
LSB Address(Byte mode)
Word/Byte selection
Chip Enable
Output Enable
Power
Data Output Power (+1.8V)
Ground
No Connection
.
.
.
.
.
.
.
.
BUFFERS
AND
DECODER
. . .
CE
OE
BHE
CONTROL
LOGIC
Q
0
/Q
8
Q
7
/Q
15
K3P7P(Q)1000B-FC
48FP-BGA PIN CONFIGURATION (TOP VIEW)
1
2
3
4
5
6
Preliminary Information
CMOS MASK ROM
A
A14
A10
N.C
A20
A6
A2
B
A13
A11
A19
N.C
A7
A3
C
A15
A12
A8
A21
A5
A4
D
D15/
A-1
Vss
A9
V
CCQ
A18
A17
OE
E
D6
V
CC
D2
D9
Vss
F
BHE
D7
D5
D10
D0
CE
G
A16
D14
D12
D11
D8
A0
H
N.C*
D13
D4
D3
D1
A1
Note : See last page for package dimension.
N.C* : will be MSB Address for the 128Mbit.
ABSOLUTE MAXIMUM RATINGS
Item
Voltage on Any Pin Relative to V
SS
Temperature Under Bias
Storage Temperature
Operating Temperature
Symbol
V
IN
T
BIAS
T
Stg
T
A
Rating
-0.3 to +4.5
-10 to +85
-55 to +150
0 to +70
Unit
V
°C
°C
°C
NOTE
: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to V
SS
, T
A
= 0 to 70°C)
Item
Supply Voltage
Supply Voltage
Supply Voltage
Symbol
V
CC
V
CCQ
V
SS
Min
2.7/3.0
1.6
0
Typ
3.0/3.3
1.8
0
Max
3.3/3.6
2.0
0
Unit
V
V
V
K3P7P(Q)1000B-FC
DC CHARACTERISTICS
Parameter
Operating Current
Standby Cur-
rent
TTL Level
CMOS Level
Symbol
I
CC
I
SB1
I
SB2
I
LI
I
LO
V
IH
V
IL
V
OH
V
OL
I
OH
= -200uA (V
CCQ
=1.8V)
I
OL
= 2.1mA
Preliminary Information
CMOS MASK ROM
Test Conditions
CE=OE=V
IL
, all outputs open
CE=V
IH
, all outputs open
CE=V
CC
, all outputs open
V
IN
=0 to V
CC
V
OUT
=0 to V
CC
Min
-
-
-
-
-
1.3
-0.3
1.4
-
Max
60
500
50
10
10
V
CC
+0.3
0.5
-
0.4
Unit
mA
uA
uA
uA
uA
V
V
V
V
Input Leakage Current
Output Leakage Current
Input High Voltage, All Inputs
Input Low Voltage, All Inputs
Output High Voltage Level
Output Low Voltage Level
NOTE
: Minimum DC Voltage(V
IL
) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input pins(V
IH
) is V
DD
+0.3V which, during transitions, may overshoot to V
DD
+2.0V for periods <20ns.
MODE SELECTION
CE
H
L
L
OE
X
H
L
BHE
X
X
H
L
Q
15
/A
-1
X
X
Output
Input
Mode
Standby
Operating
Operating
Operating
Data
High-Z
High-Z
Q
0
~Q
15
: Dout
Q
0
~Q
7
: Dout
Q
8
~Q
14
: Hi-Z
Power
Standby
Active
Active
Active
CAPACITANCE
( T
A
=25°C, f=1.0MHz)
Item
Output Capacitance
Input Capacitance
Symbol
C
OUT
C
IN
Test Conditions
V
OUT
=0V
V
IN
=0V
Min
-
-
Max
12
12
Unit
pF
pF
NOTE
: Capacitance is periodically sampled and not 100% tested.
AC CHARACTERISTICS
(T
A
=0°C to +70°C, V
CC
=3.3V/3.0V±0.3V, V
CCQ
=1.8V±0.2V, unless otherwise noted.)
TEST CONDITIONS
Item
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output timing Reference Levels
Output Loads
Value
GND to V
CCQ
3ns
V
CCQ
x 0.5V
V
CCQ
x 0.5V
1 TTL Gate and C
L
=30pF
K3P7P(Q)1000B-FC
READ CYCLE (V
CCQ
=1.8V
±
0.2V
,
C
L
=30pF )
Item
Read Cycle Time
Chip Enable Access Time
Address Access Time
Page Address Access Time
Output Enable Access Time
Output or Chip Disable to Output High-Z
Output Hold from Address Change
NOTE
: Page Address is determined as below.
Word mode (BHE=V
IH
) : A
0
, A
1,
A
2
Byte mode (BHE=V
IL
) : A
-1
, A
0
, A
1,
A
2
Preliminary Information
CMOS MASK ROM
Symbol
tRC
tACE
tAA
tPA
tOE
tDF
tOH
K3P7P(Q)1000B-FC10
Min
100
100
100
30
30
20
0
Max
Unit
ns
ns
ns
ns
ns
ns
ns
K3P7P(Q)1000B-FC
TIMING DIAGRAM
READ
ADD
A
0
~A
21
A
-1(*1)
t
ACE
CE
t
OE
OE
t
OH
D
OUT
D
0
~D
7
D
8
~D
15(*2)
VALID DATA
t
AA
Preliminary Information
CMOS MASK ROM
ADD1
t
RC
ADD2
t
DF(*3)
VALID DATA
PAGE READ
≈
CE
t
DF(*3)
OE
ADD
A
0,
A
1,
A
2
A
-1(*1)
t
AA
D
OUT
D
0
~D
7
D
8
~D
15(*2)
1 st
t
PA
VALID DATA
2 nd
3 rd
≈
VALID DATA
VALID DATA
VALID DATA
NOTES :
*1.Byte Mode only. A
-1
is Least Significant Bit Address.(BHE = V
IL
)
*2. Word Mode only.(BHE = V
IH
)
*3. t
DF
is defined as the time at which the outputs achieve the open circuit condition and is not referenced to V
OH
or V
OL
level.
≈
≈
≈
≈
ADD
A
3
~A
21
≈
≈
stm32/stm8
京公网安备 11010802033920号
EEWORLD
