K4R881869E
Overview
The RDRAM
device is a general purpose high-perfor-
mance memory device suitable for use in a broad range of
applications including computer memory, graphics, video,
and any other application where high bandwidth and low
latency are required.
The 288Mbit RDRAM devices are extremely high-speed
CMOS DRAMs organized as 16M words by 18 bits. The use
of Rambus Signaling Level (RSL) technology permits up to
1200 MHz transfer rates while using conventional system
and board design technologies. RDRAM devices are capable
of sustained data transfers up to 0.883ns per two bytes (6.7ns
per sixteen bytes).
The architecture of RDRAM devices allows the highest
sustained bandwidth for multiple, simultaneous randomly
addressed memory transactions. The separate control and
data buses with independent row and column control yield
over 95% bus efficiency. The RDRAM device's 32 banks
support up to four simultaneous transactions.
System oriented features for mobile, graphics and large
memory systems include power management, byte masking,
and x18 organization. The two data bits in the x18 organiza-
tion are general and can be used for additional storage and
bandwidth or for error correction.
Direct RDRAM
™
SAMSUNG 410
K4R881869E -
xC
xx
Figure 1: Direct RDRAM CSP Package
The 288Mbit RDRAM devices are offered in a CSP hori-
zontal package suitable for desktop as well as low-profile
add-in card and mobile applications.
Key Timing Parameters/Part Numbers
Speed
Organization
Bin
I/O
Freq.
MHz
1200
1066
800
800
1200
1066
800
800
t
RAC
(Row
Access
Time) ns
32
32P
40
45
32
32P
40
45
Features
♦
Highest sustained bandwidth per DRAM device
Part Number
- 2.4GB/s sustained data transfer rate
- Separate control and data buses for maximized
efficiency
- Separate row and column control buses for
easy scheduling and highest performance
- 32 banks: four transactions can take place simul-
taneously at full bandwidth data rates
♦
Low latency features
-CN1
512Kx18x32s
a
-CT9
-CM8
-CK8
-CN1
512Kx18x32s
-CT9
-CM8
-CK8
K4R881869E-G
b
C
c
N1
K4R881869E-GCT9
K4R881869E-GCM8
K4R881869E-GCK8
K4R881869E-F
CN1
K4R881869E-FCT9
K4R881869E-FCM8
K4R881869E-FCK8
- Write buffer to reduce read latency
- 3 precharge mechanisms for controller flexibility
- Interleaved transactions
♦
Advanced power management:
- Multiple low power states allows flexibility in power
consumption versus time to transition to active state
- Power-down self-refresh
♦
Organization: 2kbyte pages and 32 banks, x 18
a.“32s” - 32 banks which use a
“split”
bank architecture.
b.“G” - WBGA lead-free package ,
“F”
- WBGA package
c.“C” - RDRAM core uses normal power self refresh.
- x18 organization allows ECC configurations or
increased storage/bandwidth
♦
Uses Rambus Signaling Level (RSL) for up to 1200MHz
operation
Page 1
Version 1.4 Dec. 2003
K4R881869E
Direct RDRAM
™
Table 1: Pin Description
Signal
SIO1,SIO0
CMD
I/O
I/O
I
Type
CMOS
a
CMOS
a
# Pins
center
2
1
Description
Serial input/output. Pins for reading from and writing to the control regis-
ters using a serial access protocol. Also used for power management.
Command input. Pins used in conjunction with SIO0 and SIO1 for reading
from and writing to the control registers. Also used for power manage-
ment.
Serial clock input. Clock source used for reading from and writing to the
control registers
Supply voltage for the RDRAM core and interface logic.
Supply voltage for the RDRAM analog circuitry.
Supply voltage for CMOS input/output pins.
Ground reference for RDRAM core and interface.
Ground reference for RDRAM analog circuitry.
Data byte A. Nine pins which carry a byte of read or write data between
the Channel and the RDRAM device. DQA8 is not used (no connection)
by RDRAM device with a x16 organization.
Clock from master. Interface clock used for receiving RSL signals from
the Channel. Positive polarity.
Clock from master. Interface clock used for receiving RSL signals from
the Channel. Negative polarity
Logic threshold reference voltage for RSL signals
Clock to master. Interface clock used for transmitting RSL signals to the
Channel. Negative polarity.
Clock to master. Interface clock used for transmitting RSL signals to the
Channel. Positive polarity.
Row access control. Three pins containing control and address informa-
tion for row accesses.
Column access control. Five pins containing control and address informa-
tion for column accesses.
Data byte B. Nine pins which carry a byte of read or write data between
the Channel and the RDRAM device. DQB8 is not used (no connection)
by RDRAM device with a x16 organization.
SCK
V
DD
V
DDa
V
CMOS
GND
GNDa
DQA8..DQA0
I
CMOS
a
1
24
1
2
28
2
I/O
RSL
b
9
CFM
CFMN
V
REF
CTMN
CTM
RQ7..RQ5 or
ROW2..ROW0
RQ4..RQ0 or
COL4..COL0
DQB8..
DQB0
I
I
RSL
b
RSL
b
1
1
1
I
I
I
I
I/O
RSL
b
RSL
b
RSL
b
RSL
b
RSL
b
1
1
3
5
9
Total pin count per package
92
a. All CMOS signals are high-true; a high voltage is a logic one and a low voltage is logic zero.
b. All RSL signals are low-true; a low voltage is a logic one and a high voltage is logic zero.
Page 3
Version 1.4 Dec. 2003
京公网安备 11010802033920号
EEWORLD
