525R-07T datasheet, PDF - EEWORLD Datasheet

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525R-07T: DescriptionClock Generator, 250MHz, PDSO28, 0.150 INCH, MO-153, SSOP-28; CategoryThe embedded processor and controller Microcontrollers and processors; File Size234KB，10 Pages; ManufacturerIDT (Integrated Device Technology)

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525R-07T Overview

Clock Generator, 250MHz, PDSO28, 0.150 INCH, MO-153, SSOP-28

525R-07T Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	TSSOP
package instruction	SSOP,
Contacts	28
Reach Compliance Code	not_compliant
ECCN code	EAR99
JESD-30 code	R-PDSO-G28
JESD-609 code	e0
length	9.9 mm
Number of terminals	28
Maximum operating temperature	70 °C
Minimum operating temperature
Maximum output clock frequency	250 MHz
Package body material	PLASTIC/EPOXY
encapsulated code	SSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	225
Master clock/crystal nominal frequency	50 MHz
Maximum seat height	1.75 mm
Maximum supply voltage	2.25 V
Minimum supply voltage	1.6 V
Nominal supply voltage	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.635 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	3.9 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER

525R-07T Preview

PRELIMINARY DATASHEET

LVCMOS USER CONFIGURABLE CLOCK

Description

The ICS525-07/08 are the most flexible way to generate

a high-quality clock output from an inexpensive crystal

or clock input at low supply voltages. The user can

configure the device to produce nearly any output

frequency from any input frequency by grounding or

floating the select pins or by driving or hard wiring the

select pins high or low. Neither microcontroller,

software, nor device programmer are needed to set the

frequency. Using Phase-Locked Loop (PLL)

techniques, the device accepts a standard fundamental

mode, inexpensive crystal to produce output clocks up

to 250 MHz. It can also produce a highly accurate

output clock from a given input clock, keeping them

frequency locked.

For similar capability with a serial interface, use the

ICS307.

This product is intended for clock generation. It has low

output jitter (variation in the output period), but input to

output skew is not defined nor guaranteed.

ICS525-07/08

Features

•

Packaged as 28-pin SSOP (150 mil body)

•

Available in Pb (lead) free package, RoHS 5/6

compliant

•

User determines the output frequency by setting all

internal dividers

•

Eliminates need for custom oscillators

Low voltage operation

Pull-ups on all select inputs

Input crystal frequency of 5 - 27 MHz

Input clock frequency of 2 - 50 MHz

Compensated loop bandwidth

Enhanced low frequency operation (-08 version)

Low jitter

Duty cycle of 45/55 up to 250 MHz

Operating voltage of 1.8 V to 2.5 V

Ideal for oscillator replacement

Available in commercial and industrial temperature

ranges

Block Diagram

X1/ICLK

Crystal

or clock

input

Crystal

Oscillator

Reference

Divider

Phase

Comparator,

Charge

Pump,

and

Loop Filter

VCO

Divider

VDD

REF

VCO

Output

Divider

CLK

Optional crystal

capacitors

Optional crystal

capacitors

Configuration Pins

V Configuration Pins

GND

S Configuration Pins

IDT™ / ICS™

LVCMOS USER CONFIGURABLE CLOCK

ICS525-07/08

REV B 031706

ICS525-07/08

LVCMOS USER CONFIGURABLE CLOCK

CLOCK MULTIPLIER

Pin Assignment (ICS525-07)

VDD

X1/ICLK

GND

VDD

REF

CLK

GND

Pin Descriptions (ICS525-07)

Number

1, 2,

24-28

3, 4, 5

6, 23

9, 20

10 - 18

Name

R5, R6,

R0-R4

S0, S1, S2

VDD

X1/ICLK

GND

V0 - V8

CLK

REF

Type

I(PU)

Power

I(PU)

Input

Output

Pin Description

Reference divider word input pins.

Select pins for output divider. See table on page 4.

Connect to VDD.

Crystal connection. Connect to a parallel resonant fundamental crystal or input clock.

Crystal connection. Connect to a crystal or leave unconnected for clock.

Connect to ground.

VCO divider word input pins.

Power-down. Active low. Turns off entire chip when low. Clock outputs stop low.

PLL output clock.

Reference output. Buffered crystal oscillator (or clock) output.

KEY: I(PU) = Input with internal pull-up resistor; X1, X2 = crystal connections

IDT™ / ICS™

LVCMOS USER CONFIGURABLE CLOCK

ICS525-07/08 REV B 031706

ICS525-07/08

LVCMOS USER CONFIGURABLE CLOCK

CLOCK MULTIPLIER

Pin Assignment (ICS525-08)

VDD

X1/ICLK

GND

VDD

REF

CLK

GND

Pin Descriptions (ICS525-08)

Number

1, 24-28

2, 3, 4, 5

6, 23

9, 20

10 - 18

Name

R5, R0-R4

S0, S1, S2,

VDD

X1/ICLK

GND

V0 - V8

CLK

REF

Type

I(PU)

Power

I(PU)

Input

Output

Pin Description

Reference divider word input pins.

Select pins for output divider. See table on page 4.

Connect to VDD.

Crystal connection. Connect to a parallel resonant fundamental crystal or input clock.

Crystal connection. Connect to a crystal or leave unconnected for clock.

Connect to ground.

VCO divider word input pins.

Power-down. Active low. Turns off entire chip when low. Clock outputs stop low.

PLL output clock.

Reference output. Buffered crystal oscillator (or clock) output.

IDT™ / ICS™

LVCMOS USER CONFIGURABLE CLOCK

ICS525-07/08 REV B 031706

ICS525-07/08

LVCMOS USER CONFIGURABLE CLOCK

CLOCK MULTIPLIER

Output Frequency and Output Divider Table (ICS525-07)

Output Frequency Range (MHz)

S0 CLK Output

Pin 5 Pin 4 Pin 3

Divider

Min

VDD = 2.5 V

Max

20.8

125

15.63

62.5

35.7

250

83.33

VDD = 1.8 V

Min

Max

100

12.5

200

Output Frequency and Output Divider Table (ICS525-08)

Output Frequency Range (MHz)

S0 CLK Output

Pin 2 Pin 5 Pin 4 Pin 3

Divider

Min

128

21.4

18.7

16.7

13.6

11.5

10.7

8.8

7.9

3.0

1.2

VDD = 2.5 V

Max

250

167

125

100

29.4

26.3

10.4

3.9

VDD = 1.8 V

Min

21.4

18.7

16.7

13.6

11.5

10.7

8.8

7.9

3.0

1.2

Max

200

133

100

28.5

26.6

23.5

8.3

3.9

IDT™ / ICS™

LVCMOS USER CONFIGURABLE CLOCK

ICS525-07/08 REV B 031706

ICS525-07/08

LVCMOS USER CONFIGURABLE CLOCK

CLOCK MULTIPLIER

External Components/Crystal

Selection

Decoupling Capacitors

The ICS525-07/08 require two 0.01µF decoupling

capacitors to be connected between VDD and GND,

one on each side of the chip. The capacitor must be

connected close to the device to minimize lead

inductance.

ICS525-08

150MHz

400MHz

(1.8 V)

500MHz

(2.5 V)

The phase detector must be kept in its operating range

according to this equation:

250kHz

Crystal Load Capacitors

The approximate total on-chip capacitance for a crystal

is 16 pF, so a parallel resonant, fundamental mode

crystal with this value of load (correlation) capacitance

should be used. For crystals with a specified load

capacitance greater than 16 pF, crystal capacitors may

be connected from each of the pins X1 and X2 to

Ground as shown in the block diagram. The value (in

pF) of these crystal caps should be (CL -16)*2, where

CL is the crystal load capacitance in pF. These external

capacitors are only required for applications where the

exact frequency is critical. For a clock input, connect to

X1 and leave X2 unconnected (no capacitors on either).

Optimum values for

V, R,

and

are found iteratively

by applying the above equations. Choosing a smaller

value of

will give better jitter. A calculator program is

available on the ICS website to automate the process.

After determining

V, R,

and

OD,

convert them to the pin

address.

V8...0 = binary(V - 8)

Example: V = 17, V8...0 = 000001001

For the ICS525-07, R6...0 = binary(R - 2)

Example: R = 15, R6...0 = 0001101

For the ICS525-08, R5...0 - binary(R)

Example: R = 15, R5...0 = 001101

S2...0 or S3...0 is configured according to the tables on

page 4. All of the configuration pins have on-chip pull-up

resistors, so pins can be floated to generate a “1”, or

tied to ground for a “0”. They can also be driven directly

by logic signals.

Configuring the Frequency

The ICS525-07/08 output frequency is determined by

its internal dividers according to this equation:

OUT

is the feedback divider and can be 8, 9, 10, 12...519

(not 11).

For the ICS525-07,

is the reference divider and can

be 2, 3, 4...129.

For the ICS525-08,

can be 1, 2...64.

For the ICS525-07,

can be 1, 2, 3, 4, 5, 7, 12, or 16.

For the ICS525-08,

can be 2, 3, 4, 5, 7, 8, 9, 10, 11,

13, 14, 15, 17, 19, 48, or 128.

The VCO must be kept in its operating range according

to this equation:

ICS525-07

75MHz

200MHz

(1.8 V)

250MHz

(2.5 V)

Output Termination

The output driver impedance is approximately 17 ohms.

Use a 33 ohm series termination resistor on each

output to match a 50 ohm trace.

Reference Source

The initial accuracy and temperature stability of the

output frequency is determined by the reference

frequency source, the crystal, or the input clock. The

PLL will track the input frequency, so if the crystal is

running at +5 ppm the CLK frequency will also be +5

ppm. A low amplitude sinusoidal reference (such as the

1 V p-p signal from a TCXO) can be used by the AC

coupling it to the X1 pin with a 0.1 µF capacitor. The X1

pin is self-biasing.

IDT™ / ICS™

LVCMOS USER CONFIGURABLE CLOCK

ICS525-07/08 REV B 031706

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