IS61NF51218-8.5TQ datasheet, PDF

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IS61NF51218-8.5TQ: DescriptionZBT SRAM, 512KX18, 8.5ns, CMOS, PQFP100, TQFP-100; Categorystorage storage; File Size154KB，20 Pages; ManufacturerIntegrated Silicon Solution ( ISSI )

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IS61NF51218-8.5TQ Overview

ZBT SRAM, 512KX18, 8.5ns, CMOS, PQFP100, TQFP-100

IS61NF51218-8.5TQ Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Integrated Silicon Solution ( ISSI )
Parts packaging code	QFP
package instruction	TQFP-100
Contacts	100
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	8.5 ns
Maximum clock frequency (fCLK)	100 MHz
I/O type	COMMON
JESD-30 code	R-PQFP-G100
JESD-609 code	e0
length	20 mm
memory density	9437184 bit
Memory IC Type	ZBT SRAM
memory width	18
Number of functions	1
Number of terminals	100
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512KX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Encapsulate equivalent code	QFP100,.63X.87
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum standby current	0.01 A
Minimum standby current	3.14 V
Maximum slew rate	0.38 mA
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	14 mm

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IS61NF25632 IS61NF25636 IS61NF51218

IS61NLF25632 IS61NLF25636 IS61NLF51218

256K x 32, 256K x 36 and 512K x 18

FLOW-THROUGH 'NO WAIT' STATE BUS

SRAM

ISSI

PRELIMINARY INFORMATION

SEPTEMBER 2000

FEATURES

•

100 percent bus utilization

No wait cycles between Read and Write

Internal self-timed write cycle

Individual Byte Write Control

Single R/W (Read/Write) control pin

Clock controlled, registered address,

data and control

Interleaved or linear burst sequence control

using MODE input

Three chip enables for simple depth expansion

and address pipelining for TQFP

Power Down mode

Common data inputs and data outputs

CKE

pin to enable clock and suspend operation

JEDEC 100-pin TQFP, 119 PBGA package

Single +3.3V power supply (± 5%)

NF Version: 3.3V I/O Supply Voltage

NLF Version: 2.5V I/O Supply Voltage

Industrial temperature available

DESCRIPTION

The 8 Meg 'NF' product family feature high-speed,

low-power synchronous static RAMs designed to provide

a burstable, high-performance, 'no wait' state, device for

network and communications customers. They are

organized as 262,144 words by 32 bits, 262,144 words

by 36 bits and 524,288 words by 18 bits, fabricated with

ISSI

's advanced CMOS technology.

Incorporating a 'no wait' state feature, wait cycles are

eliminated when the bus switches from read to write, or

write to read. This device integrates a 2-bit burst counter,

high-speed SRAM core, and high-drive capability outputs

into a single monolithic circuit.

All synchronous inputs pass through registers are controlled

by a positive-edge-triggered single clock input. Operations

may be suspended and all synchronous inputs ignored

when Clock Enable,

CKE

is HIGH. In this state the internal

device will hold their previous values.

All Read, Write and Deselect cycles are initiated by the

ADV input. When the ADV is HIGH the internal burst

counter is incremented. New external addresses can be

loaded when ADV is LOW.

Write cycles are internally self-timed and are initiated by

the rising edge of the clock inputs and when

is LOW.

Separate byte enables allow individual bytes to be written.

A burst mode pin (MODE) defines the order of the burst

sequence. When tied HIGH, the interleaved burst sequence

is selected. When tied LOW, the linear burst sequence is

selected.

FAST ACCESS TIME

Symbol

Parameter

Clock Access Time

Cycle Time

Frequency

-8.5*

8.5

100

-9

-10

Units

MHz

*This speed available only in NF version

This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the

Integrated Silicon Solution, Inc. — 1-800-379-4774

PRELIMINARY INFORMATION

11/30/00

Rev. 00C

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