PALCE20V8H-15PI/4 datasheet, PDF

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PALCE20V8H-15PI/4: DescriptionEE PLD, 15ns, PAL-Type, CMOS, PDIP24, 0.300 INCH, SKINNY, PLASTIC, DIP-24; CategoryProgrammable logic devices Programmable logic; File Size400KB，28 Pages; ManufacturerVantis Corporation

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PALCE20V8H-15PI/4 Overview

EE PLD, 15ns, PAL-Type, CMOS, PDIP24, 0.300 INCH, SKINNY, PLASTIC, DIP-24

PALCE20V8H-15PI/4 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Vantis Corporation
package instruction	0.300 INCH, SKINNY, PLASTIC, DIP-24
Reach Compliance Code	unknown
Other features	8 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK; PROGRAMMABLE OUTPUT POLARITY
Architecture	PAL-TYPE
maximum clock frequency	45.5 MHz
JESD-30 code	R-PDIP-T24
JESD-609 code	e0
Dedicated input times	12
Number of I/O lines	8
Number of entries	20
Output times	8
Number of product terms	64
Number of terminals	24
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	12 DEDICATED INPUTS, 8 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP24,.3
Package shape	RECTANGULAR
Package form	IN-LINE
power supply	5 V
Programmable logic type	EE PLD
propagation delay	15 ns
Certification status	Not Qualified
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL

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COM'L: H-5/7/10/15/25, Q-10/15/25

IND: H-15/25, Q-20/25

PALCE20V8 Family

EE CMOS 24-Pin Universal

Programmable Array Logic

DISTINCTIVE CHARACTERISTICS

Pin and function compatible with all PAL

20V8 devices

Electrically erasable CMOS technology provides reconﬁgurable logic and full testability

High-speed CMOS technology

— 5-ns propagation delay for “-5” version

— 7.5-ns propagation delay for “-7” version

Direct plug-in replacement for a wide range of 24-pin PAL devices

Programmable enable/disable control

Outputs individually programmable as registered or combinatorial

Peripheral Component Interconnect (PCI) compliant

Preloadable output registers for testability

Automatic register reset on power-up

Cost-effective 24-pin plastic SKINNY DIP and 28-pin PLCC packages

Extensive third-party software and programmer support

Fully tested for 100% programming and functional yields and high reliability

Programmable output polarity

5-ns version utilizes a split leadframe for improved performance

PAL Devices

GENERAL DESCRIPTION

The PALCE20V8 is an advanced PAL device built with low-power, high-speed, electrically-

erasable CMOS technology. Its macrocells provide a universal device architecture. The

PALCE20V8 is fully compatible with the GAL20V8 and can directly replace PAL20R8 series

devices and most 24-pin combinatorial PAL devices.

Device logic is automatically conÞgured according to the userÕs design speciÞcation. A design is

implemented using any of a number of popular design software packages, allowing automatic

creation of a programming Þle based on Boolean or state equations. Design software also veriÞes

the design and can provide test vectors for the Þnished device. Programming can be

accomplished on standard PAL device programmers.

The PALCE20V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to

implement complex logic functions easily and efÞciently. Multiple levels of combinatorial logic

can always be reduced to sum-of-products form, taking advantage of the very wide input gates

available in PAL devices. The equations are programmed into the device through ßoating-gate

cells in the AND logic array that can be erased electrically.

Publication#

16491

Amendment/0

Rev:

Issue Date:

November 1998

CONFIGURATION OPTIONS

Each macrocell can be conÞgured as one of the following: registered output, combinatorial

output, combinatorial I/O or dedicated input. In the registered output conÞguration, the output

buffer is enabled by the OE pin. In the combinatorial conÞguration, the buffer is either controlled

by a product term or always enabled. In the dedicated input conÞguration, the buffer is always

disabled. A macrocell conÞgured as a dedicated input derives the input signal from an adjacent

I/O.

The macrocell conÞgurations are controlled by the conÞguration control word. It contains 2

global bits (SG0 and SG1) and 16 local bits (SL0

through SL0

and SL1

through SL1

). SG0

determines whether registers will be allowed. SG1 determines whether the PALCE20V8 will

emulate a PAL20R8 family or a combinatorial device. Within each macrocell, SL0

, in conjunction

with SG1, selects the conÞguration of the macrocell and SL1

sets the output as either active low

or active high.

The conÞguration bits work by acting as control inputs for the multiplexers in the macrocell.

There are four multiplexers: a product term input, an enable select, an output select, and a

feedback select multiplexer. SG1 and SL0

are the control signals for all four multiplexers. In MC

and MC

, SG0 replaces SG1 on the feedback multiplexer.

These conÞgurations are summarized in Table 1 and illustrated in Figure 2.

If the PALCE20V8 is conÞgured as a combinatorial device, the CLK and OE pins may be available

as inputs to the array. If the device is conÞgured with registers, the CLK and OE pins cannot be

used as data inputs.

Registered Output Conﬁguration

The control bit settings are SG0 = 0, SG1 = 1 and SL0

= 0. There is only one registered

conÞguration. All eight product terms are available as inputs to the OR gate. Data polarity is

determined by SL1

. SL1

is an input to the exclusive-OR gate which is the D input to the ßip-

ßop. SL1

is programmed as 1 for inverted output or 0 for non-inverted output. The ßip-ßop is

loaded on the LOW-to-HIGH transition of CLK. The feedback path is from Q on the register. The

output buffer is enabled by OE.

Combinatorial Conﬁgurations

The PALCE20V8 has three combinatorial output conÞgurations: dedicated output in a non-

registered device, I/O in a non-registered device and I/O in a registered device.

Dedicated Output in a Non-Registered Device

The control settings are SG0 = 1, SG1 = 0, and SL0

= 0. All eight product terms are available to

the OR gate. Although the macrocell is a dedicated output, the feedback is used, with the

exception of pins 18(21) and 19(23). Pins 18(21) and 19(23) do not use feedback in this mode.

Note:

1. The pin number without parentheses refers to the SKINNY DIP package. The pin number in parentheses refers to the PLCC

package.

306

PALCE20V8 Family

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