SMJS020C − OCTOBER 1994 − REVISED JANUARY 1998
TMS28F020
262144
BY 8
BIT
FLASH MEMORY
D
D
D
D
D
D
D
D
EPROMs
V
CC
Tolerance
±10%
All Inputs/Outputs TTL Compatible
Maximum Access/Minimum Cycle Time
’28F020-10
100 ns
’28F020-12
120 ns
’28F020-15
150 ns
’28F020-17
170 ns
Industry-Standard Programming Algorithm
100 000 and 10 000 Program / Erase-Cycle
Versions Available
Latchup Immunity of 250 mA on All Input
and Output Lines
Low Power Dissipation (V
CC
= 5.5 V)
− Active Write . . . 55 mW
− Active Read . . . 165 mW
− Electrical Erase . . . 82.5 mW
− Standby . . . 0.55 mW
(CMOS-Input Levels)
Automotive Temperature Range
− 40°C to 125°C
A12
A15
A16
VPP
VCC
W
A17
4
3 2 1 32 31 30
29
28
27
26
25
24
23
22
21
14 15 16 17 18 19 20
D
Organization . . . 262 144 by 8-Bits
D
Pin Compatible With Existing 2-Megabit
FM PACKAGE
( TOP VIEW )
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
5
6
7
8
9
10
11
12
13
A14
A13
A8
A9
A11
G
A10
E
DQ7
PIN NOMENCLATURE
A0 −A17
DQ0 −DQ7
E
G
VCC
VPP
VSS
W
Address Inputs
Inputs (programming) / Outputs
Chip Enable
Output Enable
5-V Power Supply
12-V Power Supply
Ground
Write Enable
description
The TMS28F020 flash memory is a 262 144 by
8-bit (2 097 152-bit), programmable read-only
memory that can be electrically bulk-erased and
reprogrammed. It is available in 100 000 and
10 000 program/erase-endurance-cycle versions.
The TMS28F020 is offered in a 32-lead plastic
leaded chip-carrier package using 1,25-mm
(50-mil) lead spacing (FM suffix) and a 32-lead
thin small-outline package (DD suffix).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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•
HOUSTON, TEXAS 77251−1443
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
Copyright
1998, Texas Instruments Incorporated
1
SMJS020C − OCTOBER 1994 − REVISED JANUARY 1998
TMS28F020
262144
BY 8
BIT
FLASH MEMORY
DD PACKAGE
( TOP VIEW )
A11
A9
A8
A13
A14
A17
W
V
CC
V
PP
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
V
SS
DQ2
DQ1
DQ0
A0
A1
A2
A3
device symbol nomenclature
TMS28F020
-12
C5
FM
L
Temperature Range Designator
L
=
0°C to 70°C
E
= − 40°C to 85°C
Q = − 40°C to 125°C
Package Designator
FM = Plastic Leaded Chip-Carrier
DD = Thin Small-Outline Package
Program/Erase Endurance
C5 = 100 000 Cycles
C4 = 10 000 Cycles
Speed Designator
-10 = 100 ns
-12 = 120 ns
-15 = 150 ns
-17 = 170 ns
2
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HOUSTON, TEXAS 77251−1443
SMJS020C − OCTOBER 1994 − REVISED JANUARY 1998
TMS28F020
262144
BY 8
BIT
FLASH MEMORY
logic symbol
†
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
E
G
W
12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
30
22
24
31
0
FLASH
MEMORY
262 144
×
8
A
0
262 143
17
G1
[PWR DWN]
G2
1, 2 EN (READ)
1C3 (WRITE)
A, 3D
∇
4
DQ0
13
A, Z4
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
14
15
17
18
19
20
21
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the FM package.
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3
SMJS020C − OCTOBER 1994 − REVISED JANUARY 1998
TMS28F020
262144
BY 8
BIT
FLASH MEMORY
functional block diagram
DQ0 −DQ7
8
VPP
W
State Control
To Array
Program / Erase
Stop Timer
Program-Voltage
Switch
STB
E
G
Chip-Enable and
Output-Enable
Logic
Data Latch
Erase-Voltage Switch
Input / Output Buffers
Command Register
STB
A
d
d
r
e
s
s
L
a
t
c
h
Column Decoder
Column Gating
A0 −A17
18
Row Decoder
2 097 152-Bit
Array Matrix
4
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HOUSTON, TEXAS 77251−1443
SMJS020C − OCTOBER 1994 − REVISED JANUARY 1998
TMS28F020
262144
BY 8
BIT
FLASH MEMORY
operation
The operation of the TMS28F020 is fully summarized in Table 1 with required signal levels shown for each
operation. The sections following the table describe operations in detail.
Table 1. Operation Modes
FUNCTION
†
MODE
Read
Output Disable
Read
Standby and Write Inhibit
Algorithm-Selection Mode
Read
Read/
Write
Output Disable
Standby and Write Inhibit
Write
VPP
‡
(1)
VPPL
VPPL
VPPL
VPPL
VPPH
VPPH
VPPH
VPPH
E
(22)
VIL
VIL
VIH
VIL
VIL
VIL
VIH
VIL
G
(24)
VIL
VIH
X
VIL
VIL
VIH
X
VIH
A0
(12)
X
X
X
VIL
VIH
X
X
X
X
A9
(26)
X
X
X
VID
X
X
X
X
W
(31)
VIH
VIH
X
VIH
VIH
VIH
X
VIL
DQ0 −DQ7
(13 −15, 17 −21)
Data Out
Hi-Z
Hi-Z
Mfr-Equivalent Code 89h
Device-Equivalent Code BDh
Data Out
Hi-Z
Hi-Z
Data In
† X can be VIL or VIH.
‡ VPPL
≤
VCC + 2 V; VPPH is the programming voltage specified for the device. For more details, refer to the recommended operating conditions.
read/output disable
When the outputs of two or more TMS28F020s are connected in parallel on the same bus, the output of any
particular device in the circuit can be read with no interference from the competing outputs of other devices. To
read the output of the TMS28F020, a low-level signal is applied to E and G. All other devices in the circuit should
have their outputs disabled by applying a high-level signal to one of these terminals.
standby and write inhibit
Active I
CC
current can be reduced from 30 mA to 1 mA by applying a high TTL level on E or to 100
µA
with a
high CMOS level on E. In this mode, all outputs are in the high-impedance state. The TMS28F020 draws active
current when it is deselected during programming, erasure, or program/erase verification. It continues to draw
active current until the operation is terminated.
algorithm-selection mode
The algorithm-selection mode provides access to a binary code identifying the correct programming and erase
algorithms. This mode is activated when A9 is forced to V
ID
. Two identifier bytes are accessed by toggling A0.
All other addresses must be held low. A0 low selects the manufacturer-equivalent code 89h, and A0 high selects
the device-equivalent code BDh, as shown in the algorithm-selection mode table below:
IDENTIFIER
§
Manufacturer-Equivalent Code
TERMINALS
A0
VIL
VIH
DQ7
1
DQ6
0
DQ5
0
DQ4
0
1
DQ3
1
1
DQ2
0
1
DQ1
0
0
DQ0
1
1
HEX
89
BD
Device-Equivalent Code
1
0
1
§ E = G = VIL, A1 −A8 = VIL, A9 = VID, A10 −A17 = VIL, VPP = VPPL.
programming and erasure
In the erased state, all bits are at a logic 1. Before erasing the device, all memory bits must be programmed to
a logic 0. Afterward, the entire chip is erased. At this point, the bits, now logic 1s, can be programmed accordingly
(refer to the Fastwrite and Fasterase algorithms for further detail).
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