ATF1502ASV-15JL44 datasheet, PDF

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ATF1502ASV-15JL44: DescriptionEE PLD, 15ns, PQCC44, PLASTIC, MS-018AC, LCC-44; CategoryProgrammable logic devices Programmable logic; File Size252KB，25 Pages; ManufacturerAtmel (Microchip); Environmental Compliance

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ATF1502ASV-15JL44 Overview

EE PLD, 15ns, PQCC44, PLASTIC, MS-018AC, LCC-44

ATF1502ASV-15JL44 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Atmel (Microchip)
Parts packaging code	LPCC
package instruction	QCCJ,
Contacts	44
Reach Compliance Code	compliant
maximum clock frequency	100 MHz
JESD-30 code	S-PQCC-J44
JESD-609 code	e3
length	16.5862 mm
Humidity sensitivity level	2
Dedicated input times
Number of I/O lines	32
Number of terminals	44
Maximum operating temperature	70 °C
Minimum operating temperature
organize	0 DEDICATED INPUTS, 32 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	245
Programmable logic type	EE PLD
propagation delay	15 ns
Certification status	Not Qualified
Maximum seat height	4.572 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	16.5862 mm

ATF1502ASV-15JL44 Preview

Features

•

High-density, High-performance, Electrically-erasable Complex Programmable

Logic Device

– 3.0 to 3.6V Operating Range

– 32 Macrocells

– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell

– 44 Pins

– 15 ns Maximum Pin-to-pin Delay

– Registered Operation up to 77 MHz

– Enhanced Routing Resources

In-System Programmability (ISP) via JTAG

Flexible Logic Macrocell

– D/T Latch Configurable Flip-flops

– Global and Individual Register Control Signals

– Global and Individual Output Enable

– Programmable Output Slew Rate

– Programmable Output Open Collector Option

– Maximum Logic Utilization by Burying a Register with a COM Output

Advanced Power Management Features

– Pin-controlled 0.75 mA Standby Mode

– Programmable Pin-keeper Inputs and I/Os

– Reduced-power Feature per Macrocell

Available in Commercial and Industrial Temperature Ranges

Available in 44-lead PLCC and TQFP

Advanced EEPROM Technology

– 100% Tested

– Completely Reprogrammable

– 10,000 Program/Erase Cycles

– 20-year Data Retention

– 2000V ESD Protection

– 200 mA Latch-up Immunity

JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported

PCI-compliant

Security Fuse Feature

Green (Pb/Halide-fee/RoHS Compliant) Package Options

•

High-

performance

EEPROM CPLD

ATF1502ASV

•

Enhanced Features

•

Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)

Output Enable Product Terms

D Latch Mode

Combinatorial Output with Registered Feedback within Any Macrocell

Three Global Clock Pins

Fast Registered Input from Product Term

Programmable “Pin-keeper” Option

Power-up Reset Option

Pull-up Option on JTAG Pins TMS and TDI

Advanced Power Management Features

– Individual Macrocell Power Option

1615J–PLD–01/06

1. Description

The ATF1502ASV is a high-performance, high-density complex programmable logic device

(CPLD) that utilizes Atmel’s proven electrically-erasable technology. With 32 logic macrocells

and up to 36 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic PLDs.

The ATF1502ASV’s enhanced routing switch matrices increase usable gate count and the odds

of successful pin-locked design modifications.

The ATF1502ASV has up to 32 bi-directional I/O pins and four dedicated input pins, depending

on the type of device package selected. Each dedicated pin can also serve as a global control

signal, register clock, register reset or output enable. Each of these control signals can be

selected for use individually within each macrocell.

Figure 1-1.

44-lead TQFP Top View

I/O

VCC

GCLK2/OE2/I

GCLR/I

I/OE1

GCLK1/I

GND

GCLK3/I/O

I/O

I/O/TDI

I/O

GND

PD1/I/O

I/O

TMS/I/O

I/O

VCC

I/O

I/O/TDO

I/O

VCC

I/O

I/O/TCK

I/O

GND

I/O

Figure 1-2.

44-lead PLCC Top View

I/O

VCC

GCLK2/OE2/I

GCLR/I

OE1/I

GCLK1/I

GND

GCLK3/I/O

I/O

ATF1502ASV

1615J–PLD–01/06

I/O

GND

VCC

I/O

PD2/I/O

I/O

TDI/I/O

I/O

GND

PD1/I/O

I/O

I/O/TMS

I/O

VCC

I/O

GND

VCC

I/O

PD2/I/O

I/O

I/O/TDO

I/O

VCC

I/O

I/O/TCK

I/O

GND

I/O

ATF1502ASV

Figure 1-3.

Block Diagram

Each of the 32 macrocells generates a buried feedback that goes to the global bus. Each input

and I/O pin also feeds into the global bus. The switch matrix in each logic block then selects 40

individual signals from the global bus. Each macrocell also generates a foldback logic term that

goes to a regional bus. Cascade logic between macrocells in the ATF1502ASV allows fast, effi-

cient generation of complex logic functions. The ATF1502ASV contains four such logic chains,

each capable of creating sum term logic with a fan-in of up to 40 product terms.

The ATF1502ASV macrocell, shown in Figure 1, is flexible enough to support highly complex

logic functions operating at high speed. The macrocell consists of five sections: product terms

and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop, output select and

enable, and logic array inputs.

Unused product terms are automatically disabled by the compiler to decrease power consump-

tion. A security fuse, when programmed, protects the contents of the ATF1502ASV. Two bytes

(16 bits) of User Signature are accessible to the user for purposes such as storing project name,

part number, revision or date. The User Signature is accessible regardless of the state of the

security fuse.

The ATF1502ASV device is an in-system programmable (ISP) device. It uses the industry stan-

dard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully compliant with JTAG’s Boundary-scan

Description Language (BSDL). ISP allows the device to be programmed without removing it from

1615J–PLD–01/06

the printed circuit board. In addition to simplifying the manufacturing flow, ISP also allows design

modifications to be made in the field via software.

Figure 1-4.

ATF1502ASV Macrocell

1.1

Product Terms and Select Mux

Each ATF1502ASV macrocell has five product terms. Each product term receives as its inputs

all signals from both the global bus and regional bus.

The product term select multiplexer (PTMUX) allocates the five product terms as needed to the

macrocell logic gates and control signals. The PTMUX programming is determined by the design

compiler, which selects the optimum macrocell configuration.

1.2

OR/XOR/CASCADE Logic

The ATF1502ASV’s logic structure is designed to efficiently support all types of logic. Within a

single macrocell, all the product terms can be routed to the OR gate, creating a 5-input AND/OR

sum term. With the addition of the CASIN from neighboring macrocells, this can be expanded to

as many as 40 product terms with little additional delay.

The macrocell’s XOR gate allows efficient implementation of compare and arithmetic functions.

One input to the XOR comes from the OR sum term. The other XOR input can be a product term

or a fixed high or low level. For combinatorial outputs, the fixed level input allows polarity selec-

tion. For registered functions, the fixed levels allow DeMorgan minimization of product terms.

The XOR gate is also used to emulate T- and JK-type flip-flops.

ATF1502ASV

1615J–PLD–01/06

ATF1502ASV

1.3

Flip-flop

The ATF1502ASV’s flip-flop has very flexible data and control functions. The data input can

come from either the XOR gate, from a separate product term or directly from the I/O pin. Select-

ing the separate product term allows creation of a buried registered feedback within a

combinatorial output macrocell. (This feature is automatically implemented by the fitter soft-

ware). In addition to D, T, JK and SR operation, the flip-flop can also be configured as a flow-

through latch. In this mode, data passes through when the clock is high and is latched when the

clock is low.

The clock itself can be either one of the Global CLK signals (GCK[0 : 2]) or an individual product

term. The flip-flop changes state on the clock’s rising edge. When the GCK signal is used as the

clock, one of the macrocell product terms can be selected as a clock enable. When the clock

enable function is active and the enable signal (product term) is low, all clock edges are ignored.

The flip-flop’s asynchronous reset signal (AR) can be either the Global Clear (GCLEAR), a prod-

uct term, or always off. AR can also be a logic OR of GCLEAR with a product term. The

asynchronous preset (AP) can be a product term or always off.

1.4

Extra Feedback

The ATF1502ASV macrocell output can be selected as registered or combinatorial.The extra

buried feedback signal can be either combinatorial or a registered signal regardless of whether

the output is combinatorial or registered. (This enhancement function is automatically imple-

mented by the fitter software.) Feedback of a buried combinatorial output allows the creation of a

second latch within a macrocell.

1.5

I/O Control

The output enable multiplexer (MOE) controls the output enable signal. Each I/O can be individ-

ually configured as an input, output or for bi-directional operation. The output enable for each

macrocell can be selected from the true or compliment of the two output enable pins, a subset of

the I/O pins, or a subset of the I/O macrocells. This selection is automatically done by the fitter

software when the I/O is configured as an input, all macrocell resources are still available,

including the buried feedback, expander and cascade logic.

1.6

Global Bus/Switch Matrix

The global bus contains all input and I/O pin signals as well as the buried feedback signal from

all 32 macrocells. The switch matrix in each logic block receives as its inputs all signals from the

global bus. Under software control, up to 40 of these signals can be selected as inputs to the

logic block.

1.7

Foldback Bus

Each macrocell also generates a foldback product term. This signal goes to the regional bus and

is available to four macrocells. The foldback is an inverse polarity of one of the macrocell’s prod-

uct terms. The four foldback terms in each region allow generation of high fan-in sum terms (up

to nine product terms) with little additional delay.

2. Programmable Pin-keeper Option for Inputs and I/Os

The ATF1502ASV offers the option of programming all input and I/O pins so that pin-keeper cir-

cuits can be utilized. When any pin is driven high or low and then subsequently left floating, it will

stay at that previous high or low level. This circuitry prevents unused input and I/O lines from

1615J–PLD–01/06

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ATF1502ASV-15JL44 Related Products

	ATF1502ASV-15JL44	ATF1502ASV-15AJ44	ATF1502ASV-15AL44
Description	EE PLD, 15ns, PQCC44, PLASTIC, MS-018AC, LCC-44	EE PLD, 15ns, PQFP44, 10 X 10 MM, 0.8 MM PITCH, 1 MM THICKNESS, PLASTIC, MS-026ACB, TQFP-44	EE PLD, 15ns, PQFP44, 10 X 10 MM, 0.8 MM PITCH, 1 MM THICKNESS, PLASTIC, MS-026ACB, TQFP-44
Is it Rohs certified?	conform to	conform to	conform to
Maker	Atmel (Microchip)	Atmel (Microchip)	Atmel (Microchip)
Parts packaging code	LPCC	QFP	QFP
package instruction	QCCJ,	TQFP,	TQFP,
Contacts	44	44	44
Reach Compliance Code	compliant	compliant	compliant
maximum clock frequency	100 MHz	100 MHz	100 MHz
JESD-30 code	S-PQCC-J44	S-PQFP-G44	S-PQFP-G44
JESD-609 code	e3	e3	e3
length	16.5862 mm	10 mm	10 mm
Humidity sensitivity level	2	3	3
Number of I/O lines	32	32	32
Number of terminals	44	44	44
Maximum operating temperature	70 °C	85 °C	70 °C
organize	0 DEDICATED INPUTS, 32 I/O	0 DEDICATED INPUTS, 32 I/O	0 DEDICATED INPUTS, 32 I/O
Output function	MACROCELL	MACROCELL	MACROCELL
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QCCJ	TQFP	TQFP
Package shape	SQUARE	SQUARE	SQUARE
Package form	CHIP CARRIER	FLATPACK, THIN PROFILE	FLATPACK, THIN PROFILE
Peak Reflow Temperature (Celsius)	245	260	260
Programmable logic type	EE PLD	EE PLD	EE PLD
propagation delay	15 ns	15 ns	15 ns
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	4.572 mm	1.2 mm	1.2 mm
Maximum supply voltage	3.6 V	3.6 V	3.6 V
Minimum supply voltage	3 V	3 V	3 V
Nominal supply voltage	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES
Temperature level	COMMERCIAL	INDUSTRIAL	COMMERCIAL
Terminal surface	Matte Tin (Sn)	Matte Tin (Sn)	Matte Tin (Sn)
Terminal form	J BEND	GULL WING	GULL WING
Terminal pitch	1.27 mm	0.8 mm	0.8 mm
Terminal location	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	40	40	40
width	16.5862 mm	10 mm	10 mm

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