FST16232 Synchronous 16-Bit to 32-Bit Multiplexer/Demultiplexer Bus Switch
July 1997
Revised December 1999
FST16232
Synchronous 16-Bit to 32-Bit
Multiplexer/Demultiplexer Bus Switch
General Description
The Fairchild Switch FST16232 is a 16-bit to 32-bit high-
speed CMOS TTL-compatible synchronous multiplexer/
demultiplexer bus switch. The low on resistance of the
switch allows inputs to be connected to outputs without
adding propagation delay or generating additional ground
bounce noise.
The device allows two separate datapaths to be multi-
plexed onto, or demultiplexed from, a single path. Two con-
trol select pins (S
1
, S
0
) are synchronous and clocked on
the rising edge of CLK when CLKEN is LOW.
Features
s
4Ω switch connection between two ports.
s
Minimal propagation delay through the switch.
s
Low l
CC
.
s
Zero bounce in flow-through mode.
s
Control inputs compatible with TTL level.
Ordering Code:
Order Number
FST16232MEA
FST16232MTD
Package Number
MS56A
MTD56
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Diagram
© 1999 Fairchild Semiconductor Corporation
DS500054
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FST16232
Connection Diagram
Pin Descriptions
Pin Name
S
1
, S
0
CLK
CLKEN
1A, 2A
1B, 2B
Description
Control Pins
Clock Input
Clock Enable Input
Bus A
Bus B
Truth Table
Inputs
S
1
X
L
L
H
H
S
0
X
L
H
L
H
CLK
X
↑
↑
↑
↑
CLKEN
H
L
L
L
L
Function
Last State
Disconnect
A = B
1
and A = B
2
A = B
1
A = B
2
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2
FST16232
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Switch Voltage (V
S
)
DC Input Voltage (V
IN
)(Note 2)
DC Input Diode Current (l
IK
) V
IN
<0V
DC Output (I
OUT
) Sink Current
DC V
CC
/GND Current (I
CC
/I
GND
)
Storage Temperature Range (T
STG
)
−0.5V
to
+7.0V
−0.5V
to
+7.0V
−0.5V
to
+7.0V
−50mA
128mA
+/−
100mA
−65°C
to
+150 °C
Recommended Operating
Conditions
(Note 3)
Power Supply Operating (V
CC)
Input Voltage (V
IN
)
Output Voltage (V
OUT
)
Input Rise and Fall Time (t
r
, t
f
)
Switch Control Input
Switch I/O
Free Air Operating Temperature (T
A
)
0nS/V to 5nS/V
0nS/V to DC
−40 °C
to
+85 °C
4.0V to 5.5V
0V to 5.5V
0V to 5.5V
Note 1:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 2:
The input and output negative voltage ratings may be exceeded if
the input and output diode current ratings are observed.
Note 3:
Unused control inputs must be held HIGH or LOW. They may not
float.
DC Electrical Characteristics
Symbol
V
IK
V
IH
V
IL
I
I
I
OFF
R
ON
Parameter
Clamp Diode Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
Input Leakage Current
OFF-STATE Leakage Current
Switch On Resistance
(Note 5)
V
CC
(V)
4.5
4.0–5.5
4.0–5.5
5.5
0
5.5
4.5
4.5
4.5
4.0
I
CC
∆
I
CC
Quiescent Supply Current
Increase in I
CC
per Input
5.5
5.5
4
4
8
11
2.0
0.8
±1.0
10
±1.0
7
7
12
20
3
2.5
T
A
= −40 °C
to
+85 °C
Min
Typ
(Note 4)
Units
Max
−1.2
V
V
V
µA
µA
µA
Ω
Ω
Ω
Ω
µA
mA
0≤ V
IN
≤5.5V
V
IN
=
5.5V
0
≤A,
B
≤V
CC
V
IN
=
0V, I
IN
=
64mA
V
IN
=
0V, I
IN
=
30mA
V
IN
=
2.4V, I
IN
=
15mA
V
IN
=
2.4V, I
IN
=
15mA
V
IN
=
V
CC
or GND, I
OUT
=
0
One input at 3.4V
Other inputs at V
CC
or GND
Note 4:
Typical values are at V
CC
=
5.0V and T
A
= +25°C
Note 5:
Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower of the
voltages on the two (A or B) pins.
Conditions
I
IN
= −18mA
3
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FST16232
AC Electrical Characteristics
T
A
= −40 °C
to
+85 °C,
Symbol
Parameter
C
L
=
50pF, RU
=
RD
=
500Ω
V
CC
=
4.5 – 5.5V
Min
f
MAX
t
PHL
, t
PLH
t
PHL
, t
PLH
t
PZH
, t
PZL
Maximum Clock Frequency
Prop Delay Bus to Bus (Note 6)
Prop Delay CLK to B or A
Output Enable Time
CLK to A
=
B
1
=
B
2
Output Enable Time
CLK to A or B
1
or B
2
t
PHZ
, t
PLZ
t
S
Output Disable Time
CLK to A or B
Setup Time S
1
, S
0
before CLK
↑
Setup Time CLKEN before CLK
↑
t
H
Hold Time S
1
, S
0
after CLK
↑
Hold Time CLKEN after CLK
↑
t
W
Pulse Width
2.0
150
0.25
6.3
Max
V
CC
=
4.0V
Min
150
0.25
6.0
Max
MHz
ns
ns
V
I
=
OPEN
V
I
=
OPEN
V
I
=
OPEN
V
I
=
7V for t
PZL
,
V
I
=
OPEN for t
PZH
V
I
=
7V for t
PZL
,
V
I
=
OPEN for t
PZH
V
I
=
7V for t
PLZ
,
V
I
=
OPEN for t
PHZ
Figure 1
Figure 2
Figure 1
Figure 2
Figure 1
Figure 2
Figure 1
Figure 2
Figure 1
Figure 2
Figure 1
Figure 2
Figure 1
Figure 2
Figure 1
Figure 2
Clock HIGH or LOW
Figure 1
Figure 2
Units
Conditions
Figure
No.
1.7
2.0
1.0
2.5
1.8
1.0
1.5
3.1
8.5
6.5
8.5
2.8
9.0
6.5
9.0
ns
ns
ns
ns
2.0
1.0
ns
1.5
3.1
ns
Note 6:
This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On
resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).
Capacitance
(Note 7)
Symbol
C
IN
C
I/O
Parameter
Control pin Input Capacitance
Input/Output Capacitance
Typ
4
7
Max
Units
pF
pF
V
CC
=
5.0V
V
CC
=
5.0V, S
0
, S
1
=
0V
Conditions
Note 7:
T
A
= +25°C,
f
=
1 MHz, Capacitance is characterized but not tested.
AC Loading and Waveforms
Note:
Input driven by 50
Ω
source terminated in 50
Ω
Note:
C
L
includes load and stray capacitance
Note:
Input PRR
=
1.0 MHz, t
W
=
500 ns
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
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4
FST16232
Physical Dimensions
inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Package Number MS56A
5
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