or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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1-1
Introduction_01.0
Lattice Semiconductor
Introduction
MachXO Family Data Sheet
The devices use look-up tables (LUTs) and embedded block memories traditionally associated with FPGAs for flex-
ible and efficient logic implementation. Through non-volatile technology the devices provide the single-chip, high-
security, instant-on capabilities traditionally associated with CPLDs. Finally, advanced process technology and
careful design provides the high pin-to-pin performance also associated with CPLDs.
The ispLEVER
®
design tools from Lattice allow complex designs to be efficiently implemented using the MachXO
family of devices. Synthesis library support for MachXO is available for popular logic synthesis tools. The
ispLEVER tools use the synthesis tool output along with the constraints from its floor planning tools to place and
route the design in the MachXO device. The ispLEVER tool extracts the timing from the routing and back-annotates
it into the design for timing verification.
1-2
MachXO Family Data Sheet
Architecture
July 2005
Advance Data Sheet
Architecture Overview
The MachXO family architecture contains an array of logic blocks surrounded by Programmable I/O (PIO). Some
devices in this family have sysCLOCK PLLs and blocks of sysMEM™ Embedded Block RAM (EBRs). Figures 2-1,
2-2 and 2-3 show the block diagrams of the various family members.
The logic blocks are arranged in a two-dimensional grid with rows and columns. The EBR blocks are arranged in a
column to the left of the logic array. The PIOs are located at the periphery of the device, arranged into banks. The
PIOs utilize a flexible I/O buffer referred to as a sysIO interface that supports operation with a variety of interface
standards. The blocks are connected with many vertical and horizontal routing channel resources. The place and
route software tool automatically allocates these routing resources.
There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and the Programmable Functional
unit without RAM/ROM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM and register
functions. The PFF block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF
blocks are optimized for flexibility, allowing complex designs to be implemented quickly and effectively. Logic blocks
are arranged in a two-dimensional array. Only one type of block is used per row.
In the MachXO family, the number of banks vary by device. There are different types of I/O Buffers on different
banks. See detail in later sections of this document. The sysMEM EBRs are large, dedicated fast memory blocks;
these blocks are found only in the larger devices. These blocks can be configured as RAM, ROM or FIFO. FIFO
support includes dedicated FIFO pointer and flag “hard” control logic to minimize LUT use.
The MachXO architecture provides up to two sysCLOCK™ Phase Locked Loop (PLL) on larger devices. These
blocks are located at either end of the memory blocks. These PLLs have multiply, divide and phase shifting capabil-
ities; they are used to manage the phase relationship of the clocks.
Every device in the family has a JTAG Port that supports programming and configuration of the device as well as
access to the user logic. The MachXO devices are available for operation from 3.3V, 2.5V, 1.8V and 1.2V power
supplies, providing easy integration into the overall system.
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
2-1
Architecture_01.0
Lattice Semiconductor
Figure 2-1. Top View of MachXO1200 Device
1
Architecture
MachXO Family Data Sheet
PIOs Arranged into
sysIO Banks
sysMEM Embedded
Block RAM (EBR)
Programmable
Functional Units
(PFUs) with RAM
Programmable
Functional Units
(PFFs) without
RAM
sysCLOCK
PLL
JTAG Port
1. Top view of MachXO2280 device is similar but with higher LUT count, two PLLs and three EBR blocks.
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