INTEGRATED CIRCUITS
PCK2023
CK408 (66/100/133/200 MHz)
spread spectrum differential system
clock generator
Product data
Supersedes data of 2001 Sep 07
2003 Jul 31
Philips
Semiconductors
Philips Semiconductors
Product data
CK408 (66/100/133/200 MHz) spread spectrum
differential system clock generator
PCK2023
FEATURES
•
3.3 V operation
•
Three differential CPU clock pairs
•
Ten PCI clocks at 3.3 V
•
Six 66 MHz clocks at 3.3 V
•
Two 48 MHz clocks at 3.3 V
•
One 14.318 MHz reference clock
•
66,100, 133 or 200 MHz operation
•
Power management control pins
•
CPU clock skew less than 200 ps cycle-to-cycle
•
CPU clock skew less than 150 ps pin-to-pin
•
1.5 ns to 3.5 ns delay on PCI pins
•
Spread Spectrum capability
DESCRIPTION
The PCK2023 is a clock synthesizer/driver for a Pentium IV and
other similar processors.
The PCK2023 has three differential pair CPU current source
outputs. There are ten PCI clock outputs running at 33 MHz and two
48 MHz clocks. There are six 3V66 outputs. Finally, there is one
3.3 V reference clock at 14.318 MHz. All clock outputs meet Intel’s
drive strength, rise/fall times, jitter, accuracy, and skew
requirements.
The part possesses a dedicated power-down input pin for power
management control. This input is synchronized on-chip and
ensures glitch-free output transitions.
PIN CONFIGURATION
V
DD
1
XTAL_In
XTAL_Out
V
SS
PCIF0
PCIF1
PCIF2
V
DD
V
SS
2
3
4
5
6
7
8
9
56 REF_0
55 S1
54 S0
53 CPU_Stop
52 CPU0
51 CPU0
50 V
DD
49 CPU1
48 CPU1
47 V
SS
46 V
DD
45 CPU2
44 CPU2
43 Mult0
42 IREF
41 V
SS
Iref
40 S2
39 USB 48 MHz
38 DOT 48 MHz
37 V
DD
48 MHz
36 V
SS
48 MHz
35 3V66_1/VCH
34 PCI_Stop
33 3V66_0
32 V
DD
31 V
SS
30 SCLK
29 SDATA
SW00695
PCI0 10
PCI1 11
PCI2 12
PCI3 13
V
DD
14
V
SS
15
PCI4 16
PCI5 17
PCI6 18
V
DD
19
V
SS
20
66Buff0/3V66_2 21
66Buff1/3V66_3 22
66Buff2/3V66_4 23
66In/3V66_5 24
PWRDWN 25
V
DD
A 26
V
SS
A 27
Vtt_Pwrgd 28
ORDERING INFORMATION
PACKAGES
56-Pin Plastic SSOP
56-Pin Plastic TSSOP
TEMPERATURE RANGE
0 to +70
°C
0 to +70
°C
ORDER CODE
PCK2023DL
PCK2023DGG
DRAWING NUMBER
SOT371-1
SOT364-1
Intel and Pentium are registered trademarks of Intel Corporation.
2003 Jul 31
2
Philips Semiconductors
Product data
CK408 (66/100/133/200 MHz) spread
spectrum differential system clock generator
PCK2023
PIN DESCRIPTION
PIN NUMBER
56
2
3
44, 45, 48, 49, 51, 52
33
35
24
21, 22, 23
5, 6, 7
10, 11, 12, 13, 16, 17,
18
39
38
40
54, 55
42
43
25
34
53
28
29
30
1, 8, 14, 19, 32, 37, 46,
50
26
4, 9, 15, 20, 31, 36, 41,
47
27
SYMBOL
ref
XTAL_In
XTAL_Out
CPU & CPU
[2:0]
3V66_0
3V66_1/VCH
66In/3V66_5
66Buff [2:0] / 3V66 [4:2]
PCIF
[2:0]
PCI
[6:0]
USB
DOT
S2
S1, S0
I
ref
Mult0
PWRDWN
PCI_Stop
CPU_Stop
Vtt_Pwrgd
SDATA
SCLOCK
V
DD
V
DD
A
V
SS
V
SS
A
3.3 V 14.318 MHz clock output.
14.318 MHz crystal input.
14.318 MHz crystal output.
Differential CPU clock outputs.
3.3 V 66 MHz clock output.
3.3 V selectable through I
2
C to be 66 MHz or 48 MHz
66 MHz input to buffered 66Buff and PCI or 66 MHz clock from internal VCO.
66 MHz buffered outputs from 66 input or 66 MHz clocks from internal VCO.
33 MHz clocks divided down from 66 input or divided down from 3V66.
PCI clock outputs divided down from 66 input or divided down from 3V66.
Fixed 48 MHz clock output.
Fixed 48 MHz clock output.
Special 3.3 V 3 level input for mode selection.
3.3 V LVTTL inputs for CPU frequency selection.
A precision resistor is attached to this pin which is connected to the internal current
reference.
3.3 V LVTTL input for selecting the current multiplier for the CPU outputs.
3.3 V LVTTL input for PowerDown active low.
3.3 V LVTTL input for PCI_Stop active low.
3.3 V LVTTL input for CPU_Stop active low.
3.3 V LVTTL input is a level sensitive strobe used to determine when S [2:0] and Mult0
inputs are valid and ok to be sampled (active low).
I
2
C compatible SDATA.
I
2
C compatible SCLOCK.
3.3 V power supply for outputs.
3.3 V power supply for PLL.
Ground for outputs.
Ground for PLL.
FUNCTION
2003 Jul 31
3
Philips Semiconductors
Product data
CK408 (66/100/133/200 MHz) spread
spectrum differential system clock generator
PCK2023
BLOCK DIAGRAM
PWRDWN
X
REF [0](14.318 MHz)
XIN X
14.318
MHZ
OSC
USBPLL
PWRDWN
X
DOT/USB 48 MHz
XOUT X
PWRDWN
SYSPLL
PWRDWN
IREF X
PWRDWN
IBIAS
X 3V66_1/VCH(48/66 MHz)
X
CPU [0-2](100/133 MHz)
X CPU [0-2](100/133 MHz)
PWRDWN
X
3V66 [2-4] (66 MHz)
CPU STOP X
PCI STOP X
PWRDWN X
S2 X
S1 X
S0 X
MULT0 X
V
tt
Pwrgd X
SDA X
SCL X
X
PCIF [0-2] (33 MHz)
PWRDWN
X
PCI [0-6](33 MHz)
LOGIC
PWRDWN
X
3V66_0 (66 MHz)
PWRDWN
X
66ln/3V66_5(66 MHz)
SW00861
2003 Jul 31
4
Philips Semiconductors
Product data
CK408 (66/100/133/200 MHz) spread
spectrum differential system clock generator
PCK2023
FREQUENCY SELECT/FUNCTION TABLE
S2
1
1
1
1
0
0
0
0
Mid
Mid
S1
0
0
1
1
0
0
1
1
0
0
S0
0
1
0
1
0
1
0
1
0
1
CPU
66 MHz
100 MHz
200 MHz
133 MHz
66 MHz
100 MHz
200 MHz
133 MHz
Low
Tclk/2
3V66
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
Hi Z
Tclk/4
66BUFF/
3V66
66 In
66 In
66 In
66 In
66 MHz
66 MHz
66 MHz
66 MHz
Hi Z
Tclk/4
66In/
3V66_5
66 input
66 input
66 input
66 input
66 MHz
66 MHz
66 MHz
66 MHz
Hi Z
Tclk/4
PCIF/PCI
66 In/2
66 In/2
66 In/2
66 In/2
33 MHz
33 MHz
33 MHz
33 MHz
Hi Z
Tclk/8
REF 0
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
Hi Z
Tclk
USB/DOT
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
Hi Z
Tclk/2
3V66_1/
VCH
66/48 MHz
66/48 MHz
66/48 MHz
66/48 MHz
66/48 MHz
66/48 MHz
66/48 MHz
66/48 MHz
Hi-Z
Tclk/4
NOTE:
1. Mid is defined as a voltage level between 1.0 V and 1.8 V for 3 level input functionality. LOW is below 0.8 V. HIGH is above 2.0 V.
2. 3V66_1/VCH output frequency is set by the I
2
C.
3. Frequency of the 48 MHz outputs must be +167 ppm to match USB default.
4. Rref output min = 14.316 MHz, nominal = 14.31818, max = 14.32 MHz.
5. Tclk is a test clock over-driven on the XTAL_In input during test mode.
POWER DOWN MODE
PWRDWN
1
0
CPU
Normal
I
ref
*2
CPU
Normal
Float
3V66
Normal
LOW
66BUFF/
3V66
Normal
LOW
66In/
3V66_5
Normal
LOW
PCIF/PCI
Normal
LOW
REF 0
Normal
LOW
USB/DOT
Normal
LOW
3V66_1/
VCH
Normal
LOW
HOST SWING SELECT FUNCTIONS - CK408
MULT 0
0
1
BOARD
IMPEDANCE
50
Ω
50
Ω
I
ref
R
ref
= 221.1%
I
ref
= 5.00 mA
R
ref
= 475.1%
I
ref
= 2.32 mA
LOAD
Nominal test load for given configuration
Nominal test load for given configuration
I
OH
I
OH
= 4*I
ref
I
OH
= 6*I
ref
V
OH
@ 50 W
1.0 V
0.7 V
CONDITIONS
I
OUT
I
OUT
V
DD
= 3.3 V
V
DD
= 3.3 V
±5%
CONFIGURATION
All combinations,
see Table above
All combinations,
see Table above
MIN.
-7% of I
OH
See Table above
-12% of I
OH
See Table above
MAX.
+7% of I
OH
See Table above
+12% of I
OH
See Table above
2003 Jul 31
5
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