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CD-700-LAC-HFB-38.880

Description
Phase Locked Loop, CQCC16, 5 X 7.50 MM, 2 MM HEIGHT, HERMETIC SEALED, CERAMIC, SMD-16
CategoryAnalog mixed-signal IC    The signal circuit   
File Size123KB,14 Pages
ManufacturerVectron International, Inc.
Websitehttp://www.vectron.com/
Environmental Compliance  
Download Datasheet Parametric View All

CD-700-LAC-HFB-38.880 Overview

Phase Locked Loop, CQCC16, 5 X 7.50 MM, 2 MM HEIGHT, HERMETIC SEALED, CERAMIC, SMD-16

CD-700-LAC-HFB-38.880 Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerVectron International, Inc.
Parts packaging codeSOIC
package instructionQCCN, LCC16,.2X.3,40
Contacts16
Reach Compliance Codecompliant
Analog Integrated Circuits - Other TypesPHASE LOCKED LOOP
JESD-30 codeR-CQCC-N16
JESD-609 codee4
length7.49 mm
Humidity sensitivity level1
Number of functions1
Number of terminals16
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeQCCN
Encapsulate equivalent codeLCC16,.2X.3,40
Package shapeRECTANGULAR
Package formCHIP CARRIER
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Certification statusNot Qualified
Maximum seat height2.13 mm
Maximum supply voltage (Vsup)3.63 V
Minimum supply voltage (Vsup)2.97 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
Temperature levelCOMMERCIAL
Terminal surfaceGold (Au) - with Nickel (Ni) barrier
Terminal formNO LEAD
Terminal pitch1.02 mm
Terminal locationQUAD
Maximum time at peak reflow temperature40
width5.08 mm
CD-700
Complete VCXO Based Phase Lock Loop
Features
5 x 7.5 x 2 mm, smallest VCXO PLL available
Output Frequencies to 77.76 MHz
5.0 or 3.3 Vdc operation
Tri-State Output
Holdover on Loss of Signal Alarm
VCXO with CMOS outputs
0/70 or –40/85
°C
temperature range
Hermetically sealed ceramic SMD package
Product is compliant to RoHS directive
Applications
Frequency Translation
Clock Smoothing, Clock Switching
LO
S
PHO OPN
(3)
(2)
OPOUT
(1)
VC
(16)
LOSIN
(4)
NRZ Clock recovery
DSLAM, ADM, ATM, Aggregation, Optical
Switching/Routing, Base Station
DATAIN
(5)
CLKIN
(6)
VCXO
Phase
Detector
and LOS
OP-Amp
Optional
2
n
Divider
OUT1
(13)
Synchronous Ethernet
Low jitter PLL’s
OUT2
(11)
Description
The VI CD-700 is a user-configurable crystal
based PLL integrated circuit. It includes a digital
phase detector, op-amp, VCXO and additional
integrated functions for use in digital
synchronization applications. Loop filter software
is available as well SPICE models for circuit
simulation.
Tel: 1-88-VECTRON-1
Web:
www.vectron.com
Rev : 06Apr08
RCLK RDATA
(9)
(10)
OPP
(15)
GND
(7)
VDD
(14)
HIZ
(12)
Figure 1. CD-700 Block Diagram
Vectron International, 267 Lowell Rd, Hudson NH 03051-4916
Page 1 of 14
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