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C8051F537A-IT

Description
8-BIT, FLASH, 25 MHz, MICROCONTROLLER, PDSO10
Categorysemiconductor    The embedded processor and controller   
File Size1MB,221 Pages
ManufacturerSILABS
Websitehttp://www.silabs.com
Download Datasheet Parametric View All

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C8051F537A-IT Overview

8-BIT, FLASH, 25 MHz, MICROCONTROLLER, PDSO10

C8051F537A-IT Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals10
Maximum operating temperature125 Cel
Minimum operating temperature-40 Cel
Maximum supply/operating voltage2.7 V
Minimum supply/operating voltage1.8 V
Rated supply voltage2.1 V
External data bus width0.0
Number of input and output buses6
Line speed25 MHz
Processing package description3 × 3 MM, MO-220VEED, DFN-10
stateACTIVE
packaging shapeSQUARE
Package SizeSMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
surface mountYes
Terminal formNO
Terminal spacing0.5000 mm
Terminal locationpair
Packaging MaterialsPlastic/Epoxy
Temperature levelAUTOMOTIVE
ADC channelYes
Address bus width0.0
Number of digits8
Maximum FCLK clock frequency25 MHz
Microprocessor typeMicrocontroller
PWM channelYes
ROM programmingFLASH
C8051F52x/F53x
8/4/2 kB ISP Flash MCU Family
Analog Peripherals
-
12-Bit ADC
Programmable throughput up to 200 ksps
Up to 6/16 external inputs
Data dependent windowed interrupt generator
Built-in temperature sensor
-
Comparator
Programmable hysteresis and response time
Configurable as wake-up or reset source
Low current
-
POR/Brownout Detector
-
Voltage Reference—1.5 and 2.2 V
(programmable)
Memory
-
8/4/2 kB Flash; In-system byte programmable in
-
Digital Peripherals
-
16/6 port I/O; push-pull or open-drain, 5 V tolerant
-
Hardware SPI™, and UART serial port
-
LIN 2.1 Controller (Master and Slave capable); no
-
-
crystal required
Three general purpose 16-bit counter/timers
Programmable 16-bit counter/timer array with three
capture/compare modules, WDT
512 byte sectors
256 bytes internal data RAM
On-Chip Debug
-
On-chip debug circuitry facilitates full-speed, non-
-
-
-
Supply Voltage 2.0 to 5.25 V
-
Built-in LDO regulator
High-Speed 8051 µC Core
-
Pipelined instruction architecture; executes 70% of
-
-
instructions in 1 or 2 system clocks
Up to
25 MIPS
throughput with
25 MHz system clock
Expanded interrupt handler
intrusive in-system debug (No emulator required)
Provides breakpoints, single stepping
Inspect/modify memory and registers
Complete development kit
Clock Sources
-
Internal oscillators: 24.5 MHz
±0.5%
accuracy sup-
-
ports UART and LIN-Master operation
External oscillator: Crystal, RC, C, or Clock
(1 or 2 pin modes)
Can switch between clock sources on-the-fly
-
Packages
-
10-Pin DFN (3 x 3 mm)
-
20-pin QFN (4 x 4 mm)
-
20-pin TSSOP
Automotive Qualified
-
Temperature Range:
–40 to +125 °C
-
Compliant to AEC-Q100
ANALOG
PERIPHERALS
A
M
U
X
DIGITAL I/O
UART
SPI
PCA
Timer 0
Timer 1
Timer 2
Port 0
CROSSBAR
12-bit
200 ksps
ADC
+
-
VOLTAGE
COMPARATOR
Port 1
LIN
TEMP
SENSOR
VREF
VREG
24.5 MHz High Precision (±0.5%) Internal Oscillator
HIGH-SPEED CONTROLLER CORE
8/4/2 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
8051 CPU
(25 MIPS)
DEBUG
CIRCUITRY
256 B SRAM
POR
WDT
Rev. 1.4 4/12
Copyright © 2012 by Silicon Laboratories
C8051F52x/F53x

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