EEWORLDEEWORLDEEWORLD

Part Number

Search

VC-400-GEF-205G-155.52MHZ

Description
ECL Output Clock Oscillator, 155.52MHz Nom, DIP-4
CategoryPassive components    oscillator   
File Size81KB,4 Pages
ManufacturerVectron International, Inc.
Websitehttp://www.vectron.com/
Download Datasheet Parametric View All

VC-400-GEF-205G-155.52MHZ Overview

ECL Output Clock Oscillator, 155.52MHz Nom, DIP-4

VC-400-GEF-205G-155.52MHZ Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerVectron International, Inc.
Reach Compliance Codecompliant
Maximum control voltage-4.5 V
Minimum control voltage-0.5 V
maximum descent time1.5 ns
Frequency Adjustment - MechanicalNO
Frequency offset/pull rate50 ppm
frequency stability20%
Manufacturer's serial numberVC-400
Installation featuresTHROUGH HOLE MOUNT
Nominal operating frequency155.52 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeECL
physical size20.32mm x 12.7mm x 10.8mm
longest rise time1.5 ns
Maximum supply voltage-5.46 V
Minimum supply voltage-4.94 V
Nominal supply voltage-5.2 V
surface mountNO
maximum symmetry55/45 %
Voltage Controlled Crystal Oscillators (VCXO’s)
VC-400/401/410/411/415 Series (CO-600V Series)
Description:
Low jitter capable, PECL output VCXO in a DIP,
Gull-wing or SMD package.
Features:
• 155.52 MHz Standard, Other Frequencies Available from
10 MHz to 170 MHz
• Jitter Performance <1 ps rms @ 155.52 MHz
• Temperature Stability to ±20 ppm -40°C to +85°C
• Aging: 10 ppm for 10 Years Typical
• ECL or PECL Output
• Complementary Output Available
• Package: Single DIP, Gull Wing, or True Surface Mount FR4
Performance Characteristics
Parameter
Standard Frequency:
Supply: C
D
G
J
Current: Single Ended Output
Complementary Output
Output Type: C
D
E
F
Rise/Fall Time (20-80%):
Symmetry (Duty Cycle):
Temperature Range:
Aging (10 years):
Jitter (12 kHz - 20 MHz):
Deviation/Stability:
Control Voltage: PECL, 3.3V
PECL, 5V
ECL, -4.5V
ECL, -5.2V
Transfer Function: PECL
ECL
Linearity (BSL):
ssb Phase Noise (@ 155.52 MHz)
(typical)
Symbol
fo
Vdd
Vdd
Vdd
Vdd
Icc
Icc
Minimum
10
4.75
3.13
-4.94
-4.27
Typical
5.0
3.3
-5.2
-4.5
Maximum
170
5.25
3.46
-5.46
-4.72
60
50
Unit
MHz
V
V
V
V
mA
mA
ECL
PECL
Complementary ECL
Complementary PECL
tr/tf
SYM
45
-40
10
0.5
See How to Order
Vc
Vc
Vc
Vc
0.3
0.5
-0.5
-0.5
Positive
Negative
see ordering information
10Hz
100Hz
1kHz
10kHz
50kHz
BW
10
20.32x12.70x10.8 mm (0.8”x0.5”x0.425”) 4 pin DIP
20.32x12.70x10.8 mm (0.8”x0.5”x0.425”) 5 pin DIP
20.32x12.70x11.43 mm (0.8”x0.5”x0.45”) 4 pin Gull wing
20.32x12.70x11.43 mm (0.8”x0.5”x0.45”) 5 pin Gull wing
20.32x13.72x5.72 mm (0.8”x0.54”x0.225”) SMD
-50
-80
-115
-135
-140
%
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
kHz
3.0
4.5
-4.5
-4.5
V
V
V
V
1
1.5
55
+85
ns
%
°C
ppm
ps
Modulation Bandwidth:
Package Size: 400
401
410
411
415
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • Web: www.vectron.com
20
What serial port is UART?
There are two most basic ways of serial communication: synchronous serial communication and asynchronous serial communication.Synchronous serial is the abbreviation of SPI (Serial Peripheral interface...
fish001 Microcontroller MCU
What is the minimum capacitance that AD7746 can measure?
Dear experts, I need help: Looking at the AD7746 data sheet, the input range is plus or minus 4pF, but my capacitive sensor output is a few tenths of a pF. Can the AD7746 measure this?...
zhangyao7751 ADI Reference Circuit
Read the good book "Operational Amplifier Parameter Analysis and LTspice Application Simulation" 01 LTspice Installation and Example Run
Thanks to the forum for providing me with this opportunity to learn LTspice in depth. I also use LTspice in my daily work, but I haven't studied it seriously yet.Installing LTspice LTspice can be down...
nemo1991 Analog electronics
Bus reset, turn off external clock!
Hardware: s3c2410 Many buses use the divided clock of 2410. After I set the relevant registers of the bus, will the register settings be lost if I turn off the clock? How do I reset the bus? Thank you...
jiashengit Embedded System
Regarding the hard drive problem!
Could any expert help me explain the principle of hard disk drive? I need to write a detailed design document of hard disk drive recently, but I am not very clear about the hard disk. Thanks!...
wangjun01 Embedded System
Hello world FPGA (cyclone4) development board experience post 03
The schematic diagram of kdy is in place~ I tried the demo written in verilog and it went smoothly~. The cyan LED color is very good~Then I wanted to try hellow world. I used NIOS and basically used t...
astwyg FPGA/CPLD

Technical ResourceMore

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1959  580  2331  1851  1394  40  12  47  38  29 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号