GS8342D10BD-450I datasheet, PDF

Datasheet> All Categories > storage> storage> GS8342D10BD-450I

GS8342D10BD-450I: DescriptionQDR SRAM, 4MX9, 0.45ns, CMOS, PBGA165, BGA-165; Categorystorage storage; File Size407KB，29 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/

Download Datasheet Parametric View All

GS8342D10BD-450I Overview

QDR SRAM, 4MX9, 0.45ns, CMOS, PBGA165, BGA-165

GS8342D10BD-450I Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	GSI Technology
Parts packaging code	BGA
package instruction	LBGA, BGA165,11X15,40
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
Maximum access time	0.45 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	450 MHz
I/O type	SEPARATE
JESD-30 code	R-PBGA-B165
length	15 mm
memory density	37748736 bit
Memory IC Type	QDR SRAM
memory width	9
Number of functions	1
Number of terminals	165
word count	4194304 words
character code	4000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	4MX9
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.5/1.8,1.8 V
Certification status	Not Qualified
Maximum seat height	1.4 mm
Maximum standby current	0.25 A
Minimum standby current	1.7 V
Maximum slew rate	0.795 mA
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	13 mm

Preview

Download Datasheet

View All

GS8342D07/10/19/37BD-450/400/350/333/300

165-Bump BGA

Commercial Temp

Industrial Temp

Features

• 2.0 Clock Latency

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• Burst of 4 Read and Write

• On-Die Termination (ODT) on Data (D), Byte Write (BW),

and Clock (K, K) inputs

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• Data Valid Pin (QVLD) Support

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

36Mb SigmaQuad-II+

Burst of 4 SRAM

450 MHz–300 MHz

1.8 V V

1.8 V and 1.5 V I/O

are just one element in a family of low power, low voltage

HSTL I/O SRAMs designed to operate at the speeds needed to

implement economical high performance networking systems.

Clocking and Addressing Schemes

The GS8342D07/10/19/37BD SigmaQuad-II+ SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer.

Each internal read and write operation in a SigmaQuad-II+ B4

RAM is four times wider than the device I/O bus. An input

data bus de-multiplexer is used to accumulate incoming data

before it is simultaneously written to the memory array. An

output data multiplexer is used to capture the data produced

from a single memory array read and then route it to the

appropriate output drivers as needed. Therefore the address

field of a SigmaQuad-II+ B4 RAM is always two address pins

less than the advertised index depth (e.g., the 4M x 8 has a 1M

addressable index).

SigmaQuad™ Family Overview

The GS8342D07/10/19/37BD are built in compliance with the

SigmaQuad-II+ SRAM pinout standard for Separate I/O

synchronous SRAMs. They are 37,748,736-bit (36Mb)

SRAMs. The GS8342D07/10/19/37BD SigmaQuad SRAMs

Parameter Synopsis

-450

tKHKH

tKHQV

2.22 ns

0.45 ns

-400

2.5 ns

0.45 ns

-350

2.86 ns

0.45 ns

-333

3.0 ns

0.45 ns

-300

3.3 ns

0.45 ns

Rev: 1.02 6/2012

1/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Recommended Resources

Zero-crossing detector circuit diagram E

Multifunctional electronic controller circuit

DC-DC converter circuit diagram composed of LT1072

Wien bridge sine oscillator circuit diagram

Electromagnet processing dimensions chart

555 bus stop indicator circuit

How does C language implement multitasking?: I am used to using assembly language to write time slices, but suddenly I wonder how to implement it in C? The requirements are not too high. If the buttons, LEDs, digital tubes, and infrared decoding...; ccxida Programming Basics

Does anyone have detailed information about S3C2440 transplantation? Share it: I am a beginner in ARM9. There are many transplantation materials on the Internet, but most of them are not very detailed. I hope the masters can give me more guidance. Thank you for sharing (*^__^*)...; lqdz68 Embedded System

What is the relationship between the op amp's supply voltage and input signal voltage?: I am using a differential op amp AD8139, the supply voltage is ±5V, the input signal is 0~8V, and it works fine. But I am worried that there may be hidden dangers, because 8V has exceeded the maximum ...; cuitzhs Analog electronics

A computer principle question: How long does it take to read a disk with 10,000 cylinders, 4 tracks per cylinder, and 2,048 sectors per track? Assume that we start reading the entire track from sector 0 of track 0, then read the en...; zhuweibing Embedded System

[IBM showcases the world's first 7nm chip] The most powerful chip in the legendary universe - EEWORLD University Hall: IBM's world's first 7nm chip demonstration : https://training.eeworld.com.cn/course/2174This test chip adds a material called "silicon germanium" (SiGe) to the 7nm transistor for the first time, repla...; chenyy Analog electronics

Optimizing power management in next-generation mobile phones: Consumers expect advanced 2.5G and 3G mobile phones to have the same form factor and battery life as existing 2G phones. 2.5G and 3G "smart" phones will also offer voice, data and multimedia features,...; zbz0529 Power technology

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components