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74LVC86APW

Description
Quad 2-input EXCLUSIVE-OR gate
File Size215KB,15 Pages
ManufacturerETC2
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74LVC86APW Overview

Quad 2-input EXCLUSIVE-OR gate

74LVC86A
Quad 2-input EXCLUSIVE-OR gate
Rev. 05.00 — 15 May 2006
Product data sheet
1. General description
The 74LVC86A provides four 2-input EXCLUSIVE-OR functions. It is a high-performance,
low power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS
compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in mixed 3.3 V and 5 V applications.
2. Features
5 V tolerant inputs for interlacing with 5 V logic
Supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Complies with JEDEC standard JESD8-B / JESD36
ESD protection:
HBM JESD22-A114-C exceeds 2000 V
CDM JESD22-C101-C exceeds 1000 V
Specified from
−40 °C
to +85
°C
and
−40 °C
to 125
°C
3. Ordering information
Table 1:
Ordering information
Package
Temperature
range
74LVC86AD
74LVC86ADB
−40 °C
to +125
°C
−40 °C
to +125
°C
Name
SO14
SSOP14
TSSOP14
DHVQFN14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic shrink small outline package; 14 leads;
body width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
plastic dual in-line compatible thermal enhanced very thin
quad flat package; no leads; 14 terminals;
body 2.5
×
3
×
0.85 mm
Version
SOT108-1
SOT337-1
SOT402-1
SOT762-1
Type number
74LVC86APW
−40 °C
to +125
°C
74LVC86ABQ
−40 °C
to +125
°C

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