FUJITSU SEMICONDUCTOR
DATA SHEET
AE1E
MEMORY
CMOS
2
×
512 K
×
16 BIT
SYNCHRONOUS DYNAMIC RAM
MB81F161622C-60/-70/-80/-80L
CMOS 2-Bank
×
524,288-Word
×
16 Bit
Synchronous Dynamic Random Access Memory
s
DESCRIPTION
The Fujitsu MB81F161622C is a CMOS Synchronous Dynamic Random Access Memory (SDRAM) containing
16,777,216 memory cells accessible in an 16-bit format. The MB81F161622C features a fully synchronous
operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which
enables high performance and simple user interface coexistence. The MB81F161622C SDRAM is designed to
reduce the complexity of using a standard dynamic RAM (DRAM) which requires many control signal timing
constraints, and may improve data bandwidth of memory as much as 5 times more than a conventional DRAM.
The MB81F161622C is ideally suited for laser printers, high resolution graphic adapters, accelerators and other
applications where an extremely large memory and bandwidth are required and where a simple interface is
needed.
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PRODUCT LINE & FEATURES
Parameter
CL - t
RCD
- t
RP
MB81F161622C
-60
3 - 3 - 3 clk min.
167 MHz max.
6.0 ns min.
5.5 ns max.
150 mA max.
1 mA max.
1 mA max.
-70
3 - 3 - 3 clk min.
143 MHz max.
7.0 ns min.
6 ns max.
130 mA max.
1 mA max.
1 mA max.
-80/-80L
3 - 3 - 3 clk min.
125 MHz max.
8.0 ns min.
6 ns max.
110 mA max.
1 mA max.
1 mA / 400 µA max.
Reference Spec
(100MHz @CL=3)
3 - 3 - 3 clk min.
100 MHz max.
10 ns min.
6 ns max.
90 mA max.
1 mA max.
1 mA max.
Clock Frequency (CL = 3)
Burst Mode Cycle Time (CL = 3)
Access Time From Clock (CL = 3)
Operating Current
Power Down Mode Current (I
CC2P
)
Self Refresh Mode Current (I
CC6
)
• Single +3.3 V Supply: +0.3 V /
−0.15
V tolerance (-60)
±0.3
V tolerance (-70/-80/-80L)
• LVTTL compatible I/O interface
• 4 K refresh cycles every 64 ms
• Dual banks operation
• Burst read/write operation and burst
read/single write operation capability
• Byte control by DQMU/DQML
• Programmable burst type, burst length,
and CAS latency
• Auto-and Self-refresh (every 15.6
µs)
• CKE power down mode
• Output Enable and Input Data Mask
• 167 MHz/143MHz/125 MHz clock frequency
MB81F161622C-60/-70/-80/-80L
s
PACKAGE
50-pin plastic TSOP (II)
Marking side
Preliminary (AE1E)
(FPT-50P-M05)
(Normal Bend)
Package and Ordering Information
– 50-pin plastic (400 mil) TSOP-II with normal bend leads, order as MB81F161622C-××FN (Std. power)
/-××LFN (Low power)
2
MB81F161622C-60/-70/-80/-80L
s
PIN ASSIGNMENTS AND DESCRIPTIONS
Preliminary (AE1E)
50-Pin TSOP (II)
(TOP VIEW)
<Normal Bend: FPT-50P-M05>
V
CC
DQ
0
DQ
1
V
SSQ
DQ
2
DQ
3
V
CCQ
DQ
4
DQ
5
V
SSQ
DQ
6
DQ
7
V
CCQ
DQML
WE
CAS
RAS
CS
A
11
A
10
/AP
A
0
A
1
A
2
A
3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
V
SS
DQ
15
DQ
14
V
SSQ
DQ
13
DQ
12
V
CCQ
DQ
11
DQ
10
V
SSQ
DQ
9
DQ
8
V
CCQ
DU
DQMU
CLK
CKE
DU
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
(Marking side)
Pin Number
1, 7, 13, 25, 38, 44
2, 3, 5, 6, 8, 9, 11, 12, 39, 40, 42,
43, 45, 46, 48, 49
4, 10, 26, 41, 47, 50
33, 37
15
16
17
18
19
20
20, 21, 22, 23, 24, 27, 28, 29, 30, 31, 32
34
35
14, 36
Symbol
V
CC
, V
CCQ
DQ
0
to DQ
15
V
SS
, V
SSQ
*
DU
WE
CAS
RAS
CS
A
11
(BA)
AP
A
0
to A
10
CKE
CLK
DQML, DQMU
Description
Supply Voltage
Data I/O
Ground
Don’t use (leave open)
Write Enable
Column Address Strobe
Row Address Strobe
Chip Select
Bank Select
Auto Precharge Enable
Address
Input
• Row: A
0
to A
10
• Column: A
0
to A
7
• Lower Byte: DQ
0
to DQ
7
• Upper Byte: DQ
8
to DQ
15
Clock Enable
Clock Input
Input Mask/Output Enable
* : These pins are connected internally in the chip.
3
MB81F161622C-60/-70/-80/-80L
s
BLOCK DIAGRAM
Preliminary (AE1E)
Fig. 1 - MB81F161622C BLOCK DIAGRAM
CLK
CLOCK
BUFFER
CKE
To each block
BANK-1
BANK-0
RAS
CS
CONTROL
SIGNAL
LATCH
COMMAND
DECODER
CAS
RAS
CAS
WE
WE
MODE
REGISTER
DRAM
CORE
(2,048
×
256
×
16)
A
0
to A
11
,
AP
ADDRESS
BUFFER/
REGISTER
ROW
ADDR.
DQML
DQMU
COLUMN
ADDRESS
COUNTER
I/O DATA
BUFFER/
REGISTER
COL.
ADDR.
I/O
V
CC
V
CCQ
V
SS
/V
SSQ
DQ
0
to
DQ
15
4
MB81F161622C-60/-70/-80/-80L
s
FUNCTIONAL TRUTHAL TABLE
(Note 1)
COMMAND TRUTH TABLE Notes 2,3,4
Function
Device Deselect
No Operation
Burst Stop
Read
Read with Auto-precharge
Write
Write with Auto-precharge
Bank Active (RAS)
Precharge Single Bank
Precharge All Banks
Mode Register Set
Notes:
*1.
*2.
*3.
*4.
*5.
*6.
*8,9
*6
*6
*7
Notes Symbol
*5
*5
DESL
NOP
BST
READ
WRIT
ACTV
PRE
PALL
MRS
*6 READA
*6 WRITA
CKE
n-1
H
H
H
H
H
H
H
H
H
H
H
n
X
X
X
X
X
X
X
X
X
X
X
CS
H
L
L
L
L
L
L
L
L
L
L
RAS CAS WE
X
H
H
H
H
H
H
L
L
L
L
X
H
H
L
L
L
L
H
H
H
L
X
H
L
H
H
L
L
H
L
L
L
Preliminary (AE1E)
A
11
A
10
A
9
, A
8
(BA) (AP)
X
X
X
V
V
V
V
V
V
X
L
X
X
X
L
H
L
H
V
L
H
L
X
X
X
X
X
X
X
V
X
X
V
A
7
to
A
0
X
X
X
V
V
V
V
V
X
X
V
V = Valid, L = Logic Low, H = Logic High, X = either L or H
All commands assume no CSUS command on previous rising edge of clock.
All commands are assumed to be valid state transitions.
All inputs are latched on the rising edge of clock.
NOP and DESL commands have the same effect on the part.
READ, READA, WRIT, and WRITA commands should only be issued after the corresponding bank has
been activated (ACTV command). Refer to STATE DIAGRAM.
*7. ACTV command should only be asserted after corresponding bank has been precharged (PRE or PALL
command).
*8. Required after power up.
*9. MRS command should only be issued after all banks have been precharged (PRE or PALL command).
Refer to STATE DIAGRAM.
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