FDG327N
October 2001
FDG327N
20V N-Channel PowerTrench
®
MOSFET
General Description
This N-Channel MOSFET has been designed
specifically to improve the overall efficiency of DC/DC
converters using either synchronous or conventional
switching PWM controllers. It has been optimized use
in small switching regulators, providing an extremely
low R
DS(ON)
and gate charge (Q
G
) in a small package.
Features
•
1.5 A, 20 V.
R
DS(ON)
= 90 mΩ @ V
GS
= 4.5 V.
R
DS(ON)
= 100 mΩ @ V
GS
= 2.5 V
R
DS(ON)
= 140 mΩ @ V
GS
= 1.8 V
•
Fast switching speed
•
Low gate charge (4.5 nC typical)
•
High performance trench technology for extremely
low R
DS(ON)
•
High power and current handling capability.
Applications
•
DC/DC converter
•
Power management
•
Load switch
S
D
D
G
Pin 1
1
2
D
D
6
5
4
SC70-6
3
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
P
D
T
J
, T
STG
Drain-Source Voltage
Gate-Source Voltage
Drain Current
– Continuous
– Pulsed
T
A
=25 C unless otherwise noted
o
Parameter
Ratings
20
±
8
(Note 1a)
Units
V
V
A
W
°C
1.5
6
0.42
0.38
-55 to +150
Power Dissipation for Single Operation
(Note 1a)
(Note 1b)
Operating and Storage Junction Temperature Range
Thermal Characteristics
R
θJA
R
θJA
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Ambient
(Note 1a)
(Note 1b)
300
333
°C/W
°C/W
Package Marking and Ordering Information
Device Marking
.27
Device
FDG327N
Reel Size
7’’
Tape width
8mm
Quantity
3000 units
©2001
Fairchild Semiconductor Corporation
FDG327N Rev C (W)
FDG327N
Electrical Characteristics
Symbol
BV
DSS
∆BV
DSS
∆T
J
I
DSS
I
GSSF
I
GSSR
T
A
= 25°C unless otherwise noted
Parameter
Drain–Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate–Body Leakage, Forward
Gate–Body Leakage, Reverse
(Note 2)
Test Conditions
V
GS
= 0 V,
I
D
= 250
µA
Min
20
Typ
Max Units
V
Off Characteristics
I
D
= 250
µA,Referenced
to 25°C
V
DS
= 16 V,
V
GS
= 8 V,
V
GS
= –8 V,
V
GS
= 0 V
V
DS
= 0 V
V
DS
= 0 V
I
D
= 250
µA
12
1
100
–100
mV/°C
µA
nA
nA
On Characteristics
V
GS(th)
∆V
GS(th)
∆T
J
R
DS(on)
I
D(on)
g
FS
Gate Threshold Voltage
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
On–Resistance
On–State Drain Current
Forward Transconductance
V
DS
= V
GS
,
0.4
0.7
–3
57
66
82
72
1.5
V
mV/°C
I
D
= 250
µA,Referenced
to 25°C
V
GS
= 4.5 V,
V
GS
= 2.5 V,
V
GS
= 1.8 V,
V
GS
= 4.5 V,
V
GS
= 4.5V,
I
D
= 1.5 A
I
D
= 1.4 A
I
D
= 1.2 A
I
D
= 1.5 A, T
J
=125°C
V
DS
= 5 V
90
100
140
115
mΩ
6
9
A
S
V
DS
= 10 V, I
D
= 1.5 A
Dynamic Characteristics
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
(Note 2)
V
DS
= 10 V,
f = 1.0 MHz
V
GS
= 0 V
423
87
48
pF
pF
pF
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
Turn–On Delay Time
Turn–On Rise Time
Turn–Off Delay Time
Turn–Off Fall Time
Total Gate Charge
Gate–Source Charge
Gate–Drain Charge
V
DD
= 10 V, I
D
= 1 A,
V
GS
= 4.5 V, R
GEN
= 6
Ω
6
6.5
14
2
12
13
29
4
6.3
ns
ns
ns
ns
nC
nC
nC
V
DS
= 10 V, I
D
= 1.5 A,
V
GS
= 4.5 V
4.5
0.89
0.95
Drain–Source Diode Characteristics and Maximum Ratings
I
S
V
SD
Maximum Continuous Drain–Source Diode Forward Current
Drain–Source Diode Forward
V
GS
= 0 V, I
S
= 0.32 A
Voltage
0.32
(Note 2)
A
V
0.75
1.2
Notes:
1.
R
θJA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. R
θJC
is guaranteed by design while R
θCA
is determined by the user's board design.
a)
300°C/W when
2
mounted on a 1in pad
of 2 oz copper.
b)
333°C/W when mounted
on a minimum pad of 2 oz
copper.
2.
Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
FDG327N Rev C (W)
FDG327N
Typical Characteristics
16
2
R
DS(ON)
, NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
V
GS
= 4.5V
3.0V
2.5V
2.0V
1.8
1.6
2.0V
1.4
2.5V
1.2
1
0.8
0
0.5
1
1.5
2
2.5
3
3.5
V
GS
= 1.8V
I
D
, DRAIN CURRENT (A)
12
1.8V
8
3.0V
3.5V
4.5V
4
0
V
DS
, DRAIN-SOURCE VOLTAGE (V)
0
4
8
I
D
, DRAIN CURRENT (A)
12
16
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
0.18
R
DS(ON)
, ON-RESISTANCE (OHM)
1.6
R
DS(ON)
, NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
I
D
= 1.5 A
V
GS
= 4.5V
1.4
I
D
= 0.8A
0.14
1.2
0.1
T
A
= 125
o
C
0.06
T
A
= 25 C
0.02
o
1
0.8
0.6
-50
-25
0
25
50
75
100
o
125
150
1
2
3
4
5
T
J
, JUNCTION TEMPERATURE ( C)
V
GS
, GATE TO SOURCE VOLTAGE (V)
Figure 3. On-Resistance Variation
withTemperature.
12
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
100
I
S
, REVERSE DRAIN CURRENT (A)
V
DS
= 5V
I
D
, DRAIN CURRENT (A)
9
T
A
=-55 C
o
25 C
125
o
C
o
V
GS
= 0V
10
T
A
= 125
o
C
1
25
o
C
0.1
-55 C
0.01
o
6
3
0.001
0
0.5
1
1.5
2
2.5
V
GS
, GATE TO SOURCE VOLTAGE (V)
0.0001
0
0.2
0.4
0.6
0.8
1
1.2
1.4
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics.
Figure 6. Body Diode Forward Voltage Variation
with Source Current and Temperature.
FDG327N Rev C (W)
FDG327N
Typical Characteristics
5
V
GS
, GATE-SOURCE VOLTAGE (V)
600
I
D
= 1.5A
V
DS
= 5V
10V
500
CAPACITANCE (pF)
15V
C
ISS
400
300
200
C
OSS
100
C
RSS
0
0
2
4
6
f = 1MHz
V
GS
= 0 V
4
3
2
1
0
Q
g
, GATE CHARGE (nC)
0
4
8
12
16
20
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics.
100
P(pk), PEAK TRANSIENT POWER (W)
10
Figure 8. Capacitance Characteristics.
I
D
, DRAIN CURRENT (A)
10
R
DS(ON)
LIMIT
1ms
10ms
100µs
8
SINGLE PULSE
R
θJA
= 333°C/W
T
A
= 25°C
6
1
V
GS
= 4.5V
SINGLE PULSE
R
θJA
= 333
o
C/W
T
A
= 25 C
0.01
0.1
1
o
100ms
1s
DC
4
0.1
2
10
100
0
0.0000 0.0001
1
0.001
0.01
0.1
1
10
100
1000
V
DS
, DRAIN-SOURCE VOLTAGE (V)
t
1
, TIME (sec)
Figure 9. Maximum Safe Operating Area.
Figure 10. Single Pulse Maximum
Power Dissipation.
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
1
D = 0.5
0.2
R
θJA
(t) = r(t) + R
θJA
R
θJA
= 333°C/W
0.1
0.1
0.05
0.02
0.01
SINGLE PULSE
P(pk
)
t
1
t
2
T
J
- T
A
= P * R
θJA
(t)
Duty Cycle, D = t
1
/ t
2
0.01
0.0001
0.001
0.01
0.1
t
1
, TIME (sec)
1
10
100
1000
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1b.
Transient thermal response will change depending on the circuit board design.
FDG327N Rev C (W)
SC70-6 Tape and Reel Data
SC70-6
Packaging
Configuration:
Figure 1.0
Customized Label
Packaging Description:
SC70-6 parts are shipped in tape. The carrier tape is
made from a dissipative (carbon filled) polycarbonate
resin. The cover tape is a multilayer film (Heat Activated
Adhesive in nature) primarily composed of polyester film,
adhesive layer, sealant, and anti-static sprayed agent.
These reeled parts in standard option are shipped with
3,000 units per 7” or 177cm diameter reel. The reels are
dark blue in color and is made of polystyrene plastic (anti-
static coated). Other option comes in 10,000 units per 13”
or 330cm diameter reel. This and some other options are
described in the Packaging Information table.
These full reels are individually barcode labeled and
placed inside a pizza box (illustrated in figure 1.0) made of
recyclable corrugated brown paper with a Fairchild logo
printing. One pizza box contains five reels maximum. And
these pizza boxes are placed inside a barcode labeled
shipping box which comes in different sizes depending on
the number of parts shipped.
Antistatic Cover Tape
F63TNR
Static Dissipative
Label
Embossed Carrier Tape
21
21
SC70-6 Packaging Information
Packaging Option
Packaging type
Qty per Reel/Tube/Bag
Reel Size
Box Dimension (mm)
Max qty per Box
Weight per unit (gm)
Weight per Reel (kg)
Note/Comments
Standard
(no flow code)
TNR
3,000
7” Dia
193x183x80
15,000
0.0055
0.1140
D87Z
TNR
10,000
13”
355x333x40
30,000
0.0055
0.3960
21
21
21
Pin 1
SC70-6
Unit Orientation
Barcode Label
Barcode
Label
355mm x 333mm x 40mm
Intermediate container for 13” reel option
Barcode Label sample
193mm x 183mm x 80mm
Pizza Box for Standard Option
Barcode
Label
QTY: 3000
SPEC:
D/C1: D9842AB QTY1:
SPEC REV:
D/C2:
QTY2:
CPN:
FAIRCHILD SEMICONDUCTOR CORPORATION
CBVK741B019
fdg6302p
FSID: FDG6302P
LOT: CBVK741B019
3000
(F63TNR)
SC70-6
Tape Leader and Trailer
Configuration:
Figure 2.0
Carrier Tape
Cover Tape
Components
Tr ailer Ta pe
300mm minimum or
75 empty pockets
Leader Tape
500mm minimum or
125 empty pockets
©2001 Fairchild Semiconductor Corporation
June 2001, Rev. D
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