,.
W
ANALOG
DEVICES
Integrated
Circuit
HighSpeedOperational
Amplifier
505
OBS
APPLICA TIONS
DIA
and
AID
Conversion
Wideband Amplifiers
Active Filters
Pulse Amplifiers
Fast Multiplier Pre-Amps
FEATURES
High Slew Rate: 120V/p.sec min
Fast Settling Time: 0.1% in 800nsec
0.01 % in 2p.sec
Low Ib: 25nA max (K)
Low Vos: 2.5mV max (K)
Low Vos Drift: 15p.vfc max (K)
Drives 1000pF
Low Price: $10.00 (100's, J)
PRODUCT DESCRIPTION
The Analog Devices ADSOS), ADSOSK and ADSOSS are
monolithic operational amplifiers that are specifically designed
for applications requiring high slew rate and fast settling time
to high accuracy. The ADSOS achieves a minimum slew rate
of
120V/l1sec,
provides an adjustable unity gain bandwidth
product of 4MHz to 10MHz, and settles to 0.1 % in 800nsec.
In addition to its superior dynamic characteristics, the ADSOS
maintains high gain, maximum offset voltage drift of lSp.V/C,
maximum bias currents of 2SnA and high output swing.
The circuit has a stable 6dB/octave rolloff for closed loop
operation. It is also capable of being externally adjusted for
up to 3SdB of additional closed loop gain at high frequencies,
without causing the small signal or large signal bandwidth to
decrease, and without increasing settling times.
The ADSOS is designed for high speed inverting applications
by using a feed-forward technique. It can drive capacitive
loads in excess of 1000pF and is short circuit protected.
The ADSOS provides performance superior to most high
speed IC op amps and comparable to modular versions.
Because of its monolithic construction, however, its cost is
significantly below that of modules, and becomes even lower
in large quantities.
All the circuits are supplied in the TO-100 package. The
ADSOS) and ADSOSK are specified for DoCto +70oC
temperature range operation; the ADSOSS for operation
from -55°C to +100°C.
OLE
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.,
lffl"-I1IJ!~"\!f
'.
H
;"",
PRODUCT HIGHLIGHTS
1.
The ADSOS achieves a minimum slew rate of
120V
/l1sec
and settles to 0.1 % in 800nsec.
2.
3.
All guaranteed parameters, including slew rate and
offset voltage drift, are 100% tested.
The ADSOS maintains low bias currents of 2SnA max
and low Vos drift of lSp.V/C max.
4.
Ease of use and predictability of operation make the
ADSOS an all-purpose amplifier that is free of the
problems found in most high frequency amplifiers.
SLEW RATE AND SETTLING TIME
Both slew rate and settling time are measures of an amplifier's
speed of response to an input. Slew rate is an inherent
characteristic of the amplifier and, thus, is generally less
subject to misinterpretation than is settling time, which is
often more dependent upon the test circuit than the
amplifier's ability to perform.
Slew rate defines the maximum rate of change of output
voltage for a large input step change and can be related to
the full power response (fp) by the relationship.
. .. .
S =
21TfpEo
. . . . . where Eo is the peak output voltage.
(continued on page
3)
Information
furnished
by Analog Devices is believed to ue
and reliable. However, no responsibility
is assumed by Analog
for its use; nor for any infringements
of patents or other rights
parties which may result from its use. No license is granted by
tion or otherwise under any patent or patent rights of Analog
accurate
Devices
of third
implica-
Devices.
Route 1 Industrial Park; P.O. Box 280; Norwood, Mass. 02062
Tel: 617/329-4700
TWX: 710/394-6577
SPECIFICATIONS
(typical@+25°Cand:!:15VDC, nless
u
otherwisenoted)
PARAMETER
OPEN LOOP GAIN
RL
= 2kil, Vo = tl0V
Over Temp Range (Tmin to Tmax)
OUTPUT CHARACTERISTICS
Voltage @ RL
=
2kn
Over Temp Range (Tmin to Tmax)
Current @ V0
=
tIOV
Short Circuit Current
j"
FREQUENCY RESPONSE
Unity Gain, Small Signal
Full Power Response
Slew Rate
Settling Time (Note 1)
to 0.1%
to 0.01 %
INPUT OFFSET VOLT AGE
Initial, RS ~ IOkn
Avg vs Temp (Tmin to Tmax)
vs Supply (T min to T max)
INPUT BIAS CURRENT
Initial
AD50S}
100,000 min (SOO,OOO
typ)
7S,OOOmin
AD505K
200,000 min (500,000 typ)
150,000 min
AD505S
100,000 min
tl0V min (t12V typ)
tl0mA
2SmA
4
-
10MHz (adjustable)
2.0MHz min (2.5MHz typ)
120V/j.Lsec min (lSOV/j.Lsec typ)
800nsec
OBS
2.0j.Lsec
Over Temp Range (min to T max)
Avg vs Temp (T min to T max)
INPUT IMPEDANCE
DC
Above 10Hz
INPUT NOISE
Voltage, 0.01 to 10Hz(p-p)
0.01 to 1.0MHz(rms)
Current, 0.01 to 10Hz(p-p)
POWER SUPPLY
Rated Performance
Operating, Derated Performance
Current, Quiescent
TEMPERATURE
RANGE
O°C to +70°C
-2SoC to +8SoC
-6SoC to +IS0°C
$IS.00
$12.00
$10.00
Rated Performance (T min to Tmax)
Operating
Storage
PRICE (Note 3)
(1-24)
(25-99)
(100-999)
75nA max (15nA typ)
100nA max
O.lnAtC
2Mn
20kn
2.5j.LV
10j.LV
O.lnA
t15V
t(5
to 20)V
max (6.0mA
typ)
8.0mA
.
2.5mV max (1.0mV typ)
15j.LVtC
max
(8j.LVtC
typ)
S.OmV max (1.0mV typ)
ISj.LVtC
150j.LV/V max
(801NN
typ)
OLE
TE
25nA rnax (l5nA typ)
40nA max
.
..
20j.LV/OC
max (lOj.Lvtc
.
typ)
80nA
max
-SSOC to +100oC (Note 2)
-5SoC to +100oC (Note 2)
$18.00
$14.40
$12.00
$21.00
$16.80
$14.00
NOTES:
;
See Figure 1 for test circuit diagram.
3 +12SoC operation is possible with a lOOoC/W heat sink.
Subject to change; refer to latest Microcircuit Price List
'Specifications same as ADSOSj
. 'Specifications same as ADSOSK
-2-
--
(continued from page
1)
Settling time is defined as the time elapsed from the
application of a fast step input to the time when the
amplifier output has entered and remained within a specified
error band that is symmetrical about the final value. Settling
time, therefore, is comprised of an initial propagation delay,
an additional time for the amplifier to slew to the vicinity of
some value of output voltage, and a time period to recover
from overload and settle within the given error band (see
Figure 1).
ADI tests for slew rate and settling time in a unity gain
configuration (RS
=
Rf
= 10kQ),
no capacitive load, and
a -10 volt to a +10 volt output swing.
The feed-forward operation of the AD505 is shown in the
block diagram in Figure 3. The DC signal is via the input
differential current amplifier, followed by a gain stage. An
external 390pF capacitor co'nnected between pins 1 and 9
makes this gain stage an integrator and optimizes settling time.
A 4700pF capacitor in series with a 100Q resistor is connected
between pins 9 and 5 (V-) to provide a lag which insures that
this portion of the amplifier rolls off to below unity gain
above the frequency at which the fast DC amplifier starts its
rolloff. The AC signal is fed forward by an external
0.02JlF
capacitor connected between pin 4 and pin 10 into the other
differential input of the fast DC amplifier.
INTEGRATING RESISTOR CAN BE SHUNTED
EXTERNALLY FOR WIDER BW AT HIGH GAIN
OBS
10k
AMPLITUDE
NOTE: AMPLITUDE
IS NOT TO SCALE
1
0,5
O,7M'
0,1%
ERROR
.,
BAND
~
Figure
1.
Settling Time of the AD505.
The full power response of the AD505 is displayed in Figure 2
for supply voltages of :!:15V and :!:10V. Note that at
Vs = :!:15V the full power response is greater than 2MHz and
that it decreases as the supply voltages are lowered.
OLE
TE
OUT
POSITIVE
INPUT
i5mV
PROVIDES
DC
BALANCE
AND CMR
AT
LOW
TIME
(M"o)
FREQUENCY
*USE OF EXTERNAL CAPACITORS SAVES
CHIP
'REAL
IMPROVES PERFORMANCE,
YIELD; LOWERS COST,
ESTATE',
Figure3.
Block Diagram of the AD505.
To help the user achieve best results with the AD505, here are
a few reminders. . . . .
(1)
Power supply bypasses should be provided as close to
the amplifier as possible to eliminate ringing due to the
inductance of power supply leads. A tantalum 10J,tF
capacitor in parallel with a ceramic
O.OlJlF
capacitor
is sufficient for this purpose (see Figure 4).
12
,
POlER
LlpJ)
=
t1L
(2)
All ground connections should be made at a single
ground point.
Keep leads short to eliminate stray impedance effects.
.
'ii
>
I
10
I
POWER UPPLY=t10V
B
'"
«
w 6
"-
f-
"
0 4
>
\
\
\
'.\
'\
1M
(3)
Figure 4 shows an optimum wiring diagram of the AD505.
'15V
1k
10k
lOOk
FREQUENCY
10M
OUTPUT
-Hz
Figure2.
Full Power Response of the AD505.
APPLICATIONS CONSIDERATIONS
The AD505 combines excellent DC characteristics and
dynamic performance with ease of application. Because it is
a wideband, fast settling amplifier, certain practical stabiliza-
tion and interconnection techniques are suggested to insure
proper operation and minimize user experimentation.
INPUT
SIGNAL
15V
COMMON
PO"'ER
COMMON
Figure
4.
WffmgDfugromoftheAD50~
-3-
I
e.
ed
.t
GENERAL PURPOSE WtDEBAND COMPENSATION
An approximate high frequency equivalent circuit of the
AD505 is shown in Figure 5. The unity gain open loop gain
bandwidth product can be adjusted over the range of 4MHz
to 10MHz by selecting resistor (RBW) which is con~ected
between pin 4 and pin 3. The lowest gain bandwidth product
The input impedance at high frequencies can be represented
by, in effect, a 350n resistor to common (the "Miller"
impedance of a 1.5pF capacitor*). This low impedance
effectively permits the amplifier to be stable (for large enough
values of Rf) even at low values of signal gain. For example,
with RBW = 0, a stable gain of 10 (20dB) can be obtained
using RS
is a result of an open circuit (RBW
=
00)
between pins 3 and
4, while the maximum is achieved by a short circuit
(RBW
=
0). Figure 6 displays the open loop frequency and
phase response of the AD505. Note that as RBW decreases
the open loop gain increases, and that the amplifier is stable
as long as the loop unity gain crossover is below 10MHz. In
=
5kn
and Rf = 50kn,
since the input impedance
of 500n dominates the 5kn source resistor. Similarly, a gain
of 50
without any reduction in bandwidth
can be
obtained using a lkn:50kn ratio.
*Zin;:::::
-
where G(w)
the RBW=
00
condition, the leading phase shift above
200kHz is a result of stray capacitance across the 20k,S1
input resistor, ;tnd can be used by the designer to increase
network stability.
Rin
RI
Eou.
Xc(w)
1
=
G(w)
2rrofoCoG(w)
.
=
350n
at f
= IMHz,
=
open
loop gain as a function
of frequency
and Xc(w)
=
reactive
capacitance of capacitor.
Note: At high frequencies, Zin is approximately constant
since f and G(w) are inverse functions of frequency.
In order to provide application flexibility and low cost, the
AD505 is externally compensated with several capacitors.
Several compensation circuits for differing conditions are
shown in Figure 7.
Rl
OBS
Figure
5.
'---,
Approximate
High Frequency Equivalent Circuit.
a
100
)
90
)1-
-
TI
I
'I.
IITfT1
I
'h..
II1I
4!1
I'o
I I 111
--hI
I
e
III 80
r-., --$' "I
'i' 70
2:
~
I-
1-
~
50
<t
60
,,
I
Of
I
11
1': " I
"
'f,.
OLE
TE
INPUT
OUTPUT
'91
GAIN
I
I
180!l I
I
I
I
I
I
I
I
I
~
I
,y f-i
v~~
50
100
390pF //~:I
4700pF
=
(a) Connection for higher gains (up to 500pF load)
10k
lu
t
10k
J.AA
fNPUT
OUTPUT
0
> 30
20
!:;
40
-
-I-
I
100
]'..
" '-
'-..I
'I,
~;~6~;/1
1
I
=
100pF
CL
0-500pF
--1
"-
'II
_u
"
10k
FREQUENCY
10
0
,,-
I
1k
11
I I
-.L....1.-
.
I I
II I
100k
H"z
-
---
1M
l'
T'1I
10M
II
(b) Connection as unity gain inverter (capacitive load)
J
(a)
)
-
220
!2
OUTPUT
-50
1\
Iwlo
390pFf
J
'Ok
~220PF
4700pF
-60
)
-70
I
w -80
Raw=r\.
\.
Raw-
(c) Connection for 100% feedback (e.g., as low-frequency
integrator)
~
-100
,
~
-90
'"
~
-110
<t
~
-120
-130
-140
)
-150
)
'M
100
'"
1k
10k
100k
FREQUENCY-Hz
\
Raw=O
10k
INPUT
OUTPUT
...
1M
390P~'
'no<
10M
i
4700pF
(b)
(d) Connection as unity gain inverter
Figure
7.
Figure6.
Open Loop Frequency and Phase Response.
Compensation Connections of AD505
for Various Conditions of Feedback.
-4-
-
----
NULLING THE AD505
The offset voltage of the AD505 is extremely small and, there-
fore, nulling is generally not required. However, should offset
nulling be desirable, Figure 8 shows a very effective, high
resolution nulling circuit that may be used without degrading
other performance parameters. This offset arrangement can
also be used to correct for any system error that may be pre-
sent, without affecting the performance of the amplifier.
-60 -50 -40 -30 -20 -10
Vo,
-
vV
7000
1800
1600
1400
1200
1000
BOO
600
400
200
10
20
30 40
I
50
I
60
I
I
70 80
I
I
90 100
TEMPERATURE - 'c
OBS
V,N
VaUT
--,
I
I
I
"5VDC
150k
15Ok
- 15VDC
-_.J-OO1,F
Figure
8.
High Resolution External Nulling Circuit.
The indicated values in Figure 8 represent one specific case
and can be easily adjusted to any particular application. If the
impedance of this network as seen from the positive terminal
of the AD505 is higher than 10k!1, it is suggested that a
O.OlJ.LF
capacitor to ground be used to bypass the network.
INPUT CHARACTERISTICS
In addition to its superior dynamic characteristics, the AD505
maintains low bias currents of 25nA max and a low Vos drift
of l5J.LVtC max.
Figure 9 displays the input bias current vs. temperature
characteristic of the AD505. Note that the bias current at
room temperature is l5nA and increases to less than 25nA
at -SSoC.
'b-nA
40
OLE
TE
Figure 10. Offset Voltage Drift of the AD505.
TYPICAL APPLICATIONS
APPlICAT~
RESISTOR
IN
r-
R2=5k
DIGITAL
INPUT
MDA-l0ZI
2.0k
DIGITAL/CURRENT
OUTPUT
Oto 10V
LOAD
CONVERTER
I
'
3]
AD505J
FS
6
'OUT
2mA
-TO
Zj-
390
P
9
500pF
4700
MDA-lOZ
;
1,
pF
-
J
-
100
pF
u
-
~~
AD505J as Fast Current-to- Voltage Converter.
Fast Output Buffer for Digital/Current Converter
In this configuration, the converter and amplifier settle to
within 0.1 % (1 LSB) in
3J.Ls,
and to within Y2LSB in
SJ.Ls,
typically. With the component values indicated, the
ADSOS
can feed load impedance of Sk!1 in parallel with SOOpF.
Interwiring capacitance between the converter output and
the amplifier input, plus the converter's output capacitance,
should be held to within lOpF if possible. When applied
with the
bipolar
version of MDA-10Z, the built-in feedback
resistor for :tlOV output is lOk!1. The 20k!1 RBW shunt
should be replaced by about Sk!1.
Although the MDA-lOZ is indicated in this example, the
ADSOS
may be used to unload converters having output
impedance values other than the MDA-10Z's l.Sk!1. For
example, when used with a 10-bit converter assembled from
J.LDAC
switches and resistor networks, the external RBW shunt
may be omitted and a 7.SkU load connected from the
summing point to ground.
30
10
.55.50
.25
-25
-50
-75
TEMPERATURE-oC
'100
r
Figure
9.
Input Bias Current vs. Temperature.
Figure 10 displays the offset voltage drift characteristic of
the
ADSOS.
Note that average temperature coefficient
of the offset voltage is approximately
2.5J.LV/oCfor
higher
temperatures and S.OJ.LV for low temperatures.
tc
-5-
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