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IDT100504S12Y

Description
Standard SRAM, 64KX4, 12ns, PDSO32, 0.300 INCH, PLASTIC, SOJ-32
Categorystorage    storage   
File Size83KB,7 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

IDT100504S12Y Overview

Standard SRAM, 64KX4, 12ns, PDSO32, 0.300 INCH, PLASTIC, SOJ-32

IDT100504S12Y Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeSOJ
package instruction0.300 INCH, PLASTIC, SOJ-32
Contacts32
Reach Compliance Codenot_compliant
ECCN codeEAR99
Maximum access time12 ns
I/O typeSEPARATE
JESD-30 codeR-PDSO-J32
JESD-609 codee0
length20.96 mm
memory density262144 bit
Memory IC TypeSTANDARD SRAM
memory width4
Humidity sensitivity level3
Negative supply voltage rating-4.5 V
Number of functions1
Number of terminals32
word count65536 words
character code64000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature
organize64KX4
Package body materialPLASTIC/EPOXY
encapsulated codeSOJ
Encapsulate equivalent codeSOJ32,.34
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialPARALLEL
power supply-4.5 V
Certification statusNot Qualified
Maximum seat height3.76 mm
surface mountYES
technologyCMOS
Temperature levelOTHER
Terminal surfaceTin/Lead (Sn85Pb15)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationDUAL
width7.62 mm
HIGH-SPEED BiCMOS
ECL STATIC RAM
256K (64K x 4-BIT) SRAM
Integrated Device Technology, Inc.
IDT10504
IDT100504
IDT101504
FEATURES:
• 65,536-words x 4-bit organization
• Address access time: 7/8/10/12/15 ns
• Low power dissipation: 1000mW (typ.)
• Guaranteed Output Hold time
• Fully compatible with ECL logic levels
• Separate data input and output
• Standard through-hole and surface mount packages
• Guaranteed-performance die available for MCMs/hybrids
DESCRIPTION:
The IDT10504, IDT100504 and IDT101504 are 262,144-
bit high-speed BiCEMOS™ ECL static random access
memories organized as 64Kx4, with separate data inputs and
outputs. All I/Os are fully compatible with ECL levels.
These devices are part of a family of asynchronous four-
bit-wide ECL SRAMs. The devices have been configured to
follow the standard ECL SRAM JEDEC pinout. Because they
are manufactured in BiCEMOS™ technology, power dissipa-
tion is greatly reduced over equivalent bipolar devices. Low
power operation provides higher system reliability and makes
possible the use of the plastic SOJ package for high-density
surface mount assembly.
The fast access time and guaranteed Output Hold time
allow greater margin for system timing variation. DataIN setup
time specified with respect to the trailing edge of Write Pulse
eases write timing allowing balanced Read and Write cycle
times.
FUNCTIONAL BLOCK DIAGRAM
A
0
DECODER
65,536-BIT
MEMORY
ARRAY
V
CC
V
EE
A
15
D
0
D
1
D
2
D
3
SENSE AMPS
AND READ/WRITE
CONTROL
Q
0
Q
1
Q
2
Q
3
WE
CS
2780 drw 01
BiCEMOS is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1992
Integrated Device Technology, Inc.
SEPTEMBER 1992
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