Integrated
Circuit
Systems, Inc.
ICS94201
Programmable System Frequency Generator for PII/III™
Recommended Application:
810/810E and Solano (815) type chipset
Output Features:
•
2 - CPUs @ 2.5V
•
13 - SDRAM @ 3.3V
•
3 - 3V66 @ 3.3V
•
8 - PCI @3.3V
•
1 - 24/48MHz@ 3.3V
•
1 - 48MHz @ 3.3V fixed
•
1 - REF @3.3V, 14.318MHz
Features:
•
Programmable ouput frequency.
•
Programmable ouput rise/fall time for PCI
and SDRAM clocks.
•
Programmable 3V66 to PCI skew.
•
Spread spectrum for EMI control
with programmable spread percentage.
•
Watchdog timer technology to reset system
if over-clocking causes malfunction.
•
Support power management through PD#.
•
Uses external 14.318MHz crystal.
•
FS pins for frequency select
Key Specifications:
•
CPU Output Jitter: <250ps
•
IOAPIC Output Jitter: <500ps
•
48MHz, 3V66, PCI Output Jitter: <500ps
•
CPU Output Skew: <175ps
•
PCI Output Skew: <500ps
•
3V66 Output Skew <175ps
•
For group skew timing, please refer to the
Group Timing Relationship Table.
Pin Configuration
VDDREF
X1
X2
GNDREF
GND3V66
3V66-0
3V66-1
3V66-2
VDD3V66
VDDPCI
1
*(FS0)PCICLK0
1
*(FS1)PCICLK1
1
*(SEL24_48#)PCICLK2
GNDPCI
PCICLK3
PCICLK4
PCICLK5
VDDPCI
PCICLK6
PCICLK7
GNDPCI
PD#
SCLK
SDATA
VDDSDR
SDRAM11
SDRAM10
GNDSDR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
REF0(FS4)*
VDDLAPIC
IOAPIC
VDDLCPU
CPUCLK0
CPUCLK1
GNDLCPU
GNDSDR
SDRAM0
SDRAM1
SDRAM2
VDDSDR
SDRAM3
SDRAM4
SDRAM5
GNDSDR
SDRAM6
SDRAM7
SDRAM_F
VDDSDR
GND48
24_48MHz(FS2)*
1
48MHz(FS3)*
VDD48
VDDSDR
SDRAM8
SDRAM9
GNDSDR
1
56-Pin 300 mil SSOP
1. These pins will have 1.5 to 2X drive strength.
* 120K ohm pull-up to VDD on indicated inputs.
Block Diagram
PLL2
/2
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
48MHz
24_48MHz
ICS94201
REF0
CPU
DIVDER
2
CPUCLK [1:0]
SDRAM
DIVDER
12
SDRAM [11:0]
SDRAM_F
FS[4:0]
PD#
SEL24_48#
SDATA
SCLK
Control
Logic
Config.
Reg.
IOAPIC
DIVDER
IOAPIC
PCI
DIVDER
8
PCICLK [7:0]
3V66
DIVDER
3
3V66 [2:0]
0428B- 11/28/05
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
ICS94201
General Description
The
ICS94201
is a single chip clock solution for desktop designs using the 810/810E and Solano style chipset. It provides all necessary
clock signals for such a system.
The
ICS94201
belongs to ICS new generation of programmable system clock generators. It employs serial programming I
2
C interface
as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring output to output skew,
changing spread spectrum amount, changing group divider ratio and dis/enabling individual clocks. This device also has ICS
propriety 'Watchdog Timer' technology which will reset the frequency to a safe setting if the system become unstable from over
clocking.
Spread spectrum typically reduces system EMI by 7dB to 8dB. This simplifies EMI qualification without resorting to board design
iterations or costly shielding.
Pin Configuration
PI N
PI N N A M E
N U M B ER
1, 9, 10, 18, 25,
VDD
32, 33, 37, 45
2
3
4 , 5 , 14 , 2 1 ,
28, 29, 36,
41, 49
8, 7, 6
11
12
X1
X2
GN D
3V66 [2:0]
PC IC LK 0
1
FS0
PCICLK1
1
FS1
SEL_24_48#
13
PCICLK2
1
20, 19, 17,
16, 15
22
23
24
34
PC IC LK [7:3]
OUT
O UT
3.3V PC I clock output, with Synchronous C PUC LK s
3.3V PC I clock outputs, with Synchronous C PUC LK s
Asynchronous active low input pin used to power down the device into a
low power state. The internal clocks are disabled and the VC O and the
crystal are stopped. The latency of the power down will not be greater
than 3ms.
Clock input of I
2
C input
Data input for I
2
C serial input.
Logic input frequency select bit. Input latched at power on.
3.3V Fixed 48MHz clock output for USB
Logic input frequency select bit. Input latched at power on.
3.3V 24_48MHz output, selectable through pin 13, default is 24MHz.
3.3V SDRAM output can be turned off through I
2
C
3.3V output. All SDRAM outputs can be turned off through I
2
C
Ground for 2.5V power supply for C PU & APIC
2.5V Host bus clock output. O utput frequency derived from FS pins.
2.5V power suypply for C PU, IO APIC
2.5V clock outputs running at 16.67MHz.
Logic input frequency select bit. Input latched at power on.
3.3V, 14.318MHz reference clock output.
TYPE
PWR
IN
O UT
PWR
O UT
O UT
IN
OUT
IN
IN
3.3V power supply
C rystal input, has internal load cap (33pF) and feedback
resistor from X2
C rystal output, nominally 14.318MHz. Has internal load
cap (33pF)
Ground pins for 3.3V supply
3.3V Fixed 66MHz clock outputs for HUB
3.3V PC I clock output, with Synchronous C PUC LK s
Logic input frequency select bit. Input latched at power on.
3.3V PC I clock output, with Synchronous C PUC LK s
Logic input frequency select bit. Input latched at power on.
Logic input to select output.
D E S C R I PT I O N
PD#
SCLK
SDATA
FS3
48MHz
FS2
24_48MHz
SDRAM_F
SDRAM [11:0]
GN DL
C PUC LK [1:0]
VDDL
IO APIC
FS4
REF0
1
IN
IN
O UT
IN
O UT
IN
OUT
O UT
O UT
PWR
O UT
PWR
O UT
IN
O UT
35
38
48, 47, 46, 44,
43, 42, 40, 39,
3 1, 3 0 , 2 7 , 2 6
50
5 1, 5 2
53, 55
54
56
0428B - 11/28/05
2
ICS94201
General I
2
C serial interface information for the ICS94201
How to Write:
•
•
•
•
•
•
•
•
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends a dummy command code
ICS clock will
acknowledge
Controller (host) sends a dummy byte count
ICS clock will
acknowledge
Controller (host) starts sending
Byte 0 through Byte 28
(see Note 2)
• ICS clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the
byte count
Controller (host) acknowledges
ICS clock sends
Byte 0 through byte 6 (default)
ICS clock sends
Byte 0 through byte X (if X
(H)
was
written to byte 6).
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
•
•
•
•
•
•
•
How to Write:
Controller (Host)
Start Bit
Address D2
(H)
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
ICS (Slave/Receiver)
How to Read:
Controller (Host)
Start Bit
Address D3
(H)
ICS (Slave/Receiver)
ACK
ACK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
If 7
H
has been written to B6
ACK
Byte 7
Byte 26
ACK
Byte 27
ACK
Byte 28
ACK
Stop Bit
*See notes on the following page
.
0428B - 11/28/05
If 1A
H
has been written to B6
ACK
If 1B
H
has been written to B6
ACK
If 1C
H
has been written to B6
ACK
Stop Bit
Byte26
Byte 27
Byte 28
3
ICS94201
Brief I
2
C registers description for ICS94201
Programmable System Frequency Generator
Register Name
Func tionality & Frequenc y Select
Register
Output Control Registers
Byte Count Read Back Register
Byte
0
1-5
6
Description
Output frequency, hardware / I C frequency
select, s pread spectrum & output enable
control register.
Active / inactive output control registers.
2
Pw d Default
See individual byte
des cription
See individual byte
des cription
W riting to this register will c onfigure by te
count and how many byte will be read back.
06
H
Do not write 00
H
to this byte.
Latc hed Inputs Read Back
The inverse of the latched inputs level could
See individual byte
7
des cription
Register
be read back from this regis ter.
W atchdog enable, watchdog status and
000,0000
W atchdog Control Regis ters
8 Bit[6:0] program mable 'safe' frequenc y' can be
configured in this register.
This bit selects whether the output
0
VCO Control S election B it
8 Bit[7] frequenc y is controled by hardware/by te 0
configurations or byte 14&15 programm ing.
W riting to this register will c onfigure the
FF
H
W atchdog Tim er Count Register
9
number of seconds for the watchdog timer
to reset.
This is an unused register. W riting to this
ICS Reserved Register
10
00
H
register will not affect device functionality.
Byte 11 bit[3:0] is ICS vendor id - 0001.
Device ID, Vendor ID & Revision ID
See individual byte
11-12 Other bits in these 2 registers designate
des cription
Registers
device revision ID of this part.
Don't write into this register, writing 1's will
ICS Reserved Register
13
00
H
cause m alfunction.
These registers control the dividers ratio
Depend on
hardware/byte 0
VCO Frequenc y Control Registers
14-15 into the phase detector and thus control the
configuration
VCO output frequency.
Spread Spectrum Control
Registers
16-17
These registers control the s pread
percentage amount.
Changing bits in these regis ters result in
frequenc y divider ratio changes. Incorrect
configuration of group output divider ratio
can cause system malfunction.
Increment or decrement the group skew
amount as compared to the initial skew.
These registers will control the group rise
and fall time.
Depend on
hardware/byte 0
configuration
Depend on
hardware/byte 0
configuration
See individual byte
des cription
See individual byte
des cription
Output Dividers Control Registers
18-20
Group Skews Control Registers
Output Rise/Fall Time S elect
Registers
21-23
24
Notes:
1.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches for
verification. Readback will support standard SMBUS controller protocol.
The number of bytes to read back is defined
by writing to byte 6.
When writing to bytes 14 - 15, bytes 16 - 17 and bytes 18 - 20, they must be written as a set.
If for example, only byte
14 is written but not 15, neither byte 14 or 15 will load into the receiver.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8-bit bytes.
To simplify the clock generator I
2
C interface, the protocol is set to use only Block-Writes from the controller. The bytes
must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has
been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
2.
3.
4.
5.
6.
7.
0428B - 11/28/05
4
ICS94201
Byte 0: Functionality and frequency select register (Default=0)
Bit
Bit2 Bit7 Bit6 Bit5 Bit4 VCO/REF
Divider
FS4 FS3 FS2 FS1 FS0
Description
VCO
MHz
VCO/ CPUCLK SDRAM
CPU
MHz
MHz
66.43
60.00
66.80
68.33
70.00
75.00
80.00
83.00
99.65
90.00
100.23
103.00
105.00
110.00
115.00
200.00
132.86
166.67
133.64
137.00
140.00
145.00
150.00
160.00
132.86
166.67
133.64
137.00
140.00
145.00
150.00
160.00
99.65
90.00
100.20
102.50
105.00
112.50
120.00
124.50
99.65
90.00
100.23
103.00
105.00
110.00
115.00
200.00
132.86
166.67
133.64
137.00
140.00
145.00
150.00
160.00
99.65
125.00
100.23
102.75
105.00
108.75
112.50
120.00
3V66
MHz
66.43
60.00
66.80
68.33
70.00
75.00
80.00
83.00
66.43
60.00
66.84
68.67
70.00
73.33
76.67
133.33
66.43
83.34
66.82
68.50
70.00
72.50
75.00
80.00
66.93
83.34
66.82
68.50
70.00
72.50
75.00
80.00
PCICLK
MHz
33.21
30.00
33.40
34.17
35.00
37.50
40.00
41.50
33.21
30.00
33.41
34.33
35.00
36.67
38.33
66.66
33.21
41.67
33.41
34.25
35.00
36.25
37.50
40.00
33.21
41.67
33.41
34.25
35.00
36.25
37.50
40.00
IOAPIC
MHz
16.61
15.00
16.70
17.08
17.50
18.75
20.00
20.75
16.61
15.00
16.70
17.17
17.50
18.33
19.17
33.33
16.61
20.83
16.70
17.13
17.50
18.13
18.75
20.00
16.61
20.83
16.7
17.13
17.50
18.13
18.75
20.00
PWD
Bit
(2,7:4)
Bit 3
Bit 1
Bit 0
0
0
0
0
0
501/18
398.52
6
0
0
0
0
1
352/14
360.00
6
0
0
0
1
0
504/18
400.91
6
0
0
0
1
1
315/11
410.02
6
0
0
1
0
0
440/15
420.00
6
0
0
1
0
1
440/14
450.00
6
0
0
1
1
0
503/15
480.14
6
0
0
1
1
1
313/9
497.95
6
0
1
0
0
0
515/37
199.29
2
0
1
0
0
1
440/35
180.29
2
0
1
0
1
0
518/37
200.45
2
0
1
0
1
1
446/31
206.00
2
0
1
1
0
0
484/33
210.00
2
0
1
1
0
1
507/33
219.98
2
0
1
1
1
0
514/32
229.99
2
0
1
1
1
1
447/16
400.01
2
1
0
0
0
0
501/18
398.52
3
1
0
0
0
1
454/13
500.03
3
1
0
0
1
0
504/18
400.91
3
1
0
0
1
1
488/17
411.02
3
1
0
1
0
0
440/15
420.00
3
395/13
435.05
3
1
0
1
0
1
1
0
1
1
0
440/14
450.00
3
1
0
1
1
1
503/15
480.14
3
501/18
398.52
3
1
1
0
0
0
1
1
0
0
1
454/13
500.03
3
1
1
0
1
0
504/18
400.91
3
411.02
3
1
1
0
1
1
488/17
1
1
1
0
0
440/15
420.00
3
1
1
1
0
1
395/13
435.05
3
450.00
3
1
1
1
1
0
440/14
1
1
1
1
1
503/15
480.14
3
0-Frequency is selected by hardware select, latched inputs
1- Frequency is selected by Bit 2,7:4
0- Normal
1- Spread spectrum enable ± 0.35% Center Spread
0- Running
1- Tristate all outputs
Note 1
0
1
0
Notes:
1.
Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
0428B - 11/28/05
5
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