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MT5C2565-20L

Description
Standard SRAM, 64KX4, 20ns, CMOS, PDIP28, 0.300 INCH, PLASTIC, DIP-28
Categorystorage    storage   
File Size143KB,12 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Download Datasheet Parametric View All

MT5C2565-20L Overview

Standard SRAM, 64KX4, 20ns, CMOS, PDIP28, 0.300 INCH, PLASTIC, DIP-28

MT5C2565-20L Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerMicron Technology
Parts packaging codeDIP
package instruction0.300 INCH, PLASTIC, DIP-28
Contacts28
Reach Compliance Codenot_compliant
ECCN codeEAR99
Maximum access time20 ns
I/O typeCOMMON
JESD-30 codeR-PDIP-T28
JESD-609 codee0
length36.83 mm
memory density262144 bit
Memory IC TypeSTANDARD SRAM
memory width4
Number of functions1
Number of ports1
Number of terminals28
word count65536 words
character code64000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize64KX4
Output characteristics3-STATE
ExportableYES
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP28,.3
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Certification statusNot Qualified
Maximum seat height4.32 mm
Maximum standby current0.0003 A
Minimum standby current2 V
Maximum slew rate0.15 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width7.62 mm
OBSOLETE 3/1/95
MT5C2565
64K x 4 SRAM
SRAM
FEATURES
• High speed: 10, 12, 15, 20 and 25
• High-performance, low-power, CMOS double-metal
process
• Single +5V
±10%
power supply
• Easy memory expansion with
?
C
/
E and
?
O
/
E options
• All inputs and outputs are TTL-compatible
64K x 4 SRAM
WITH OUTPUT ENABLE
PIN ASSIGNMENT (Top View)
28-Pin SOJ
(SD-2)
NC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
CE
OE
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
A15
A14
A13
A12
A11
A10
NC
NC
DQ4
DQ3
DQ2
DQ1
WE
28-Pin DIP
(SA-4)
NC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
CE
OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
A15
A14
A13
A12
A11
A10
NC
NC
DQ4
DQ3
DQ2
DQ1
WE
OPTIONS
• Timing
10ns access
12ns access
15ns access
20ns access
25ns access
• Packages
Plastic DIP (300 mil)
Plastic SOJ (300 mil)
• 2V data retention (optional)
• Low power (optional)
MARKING
-10
-12
-15
-20
-25
None
DJ
L
P
None
IT
AT
XT
• Temperature
Commercial (0°C to +70°C)
Industrial
(-40°C to +85°C)
Automotive (-40°C to +125°C)
Extended
(-55°C to +125°C)
Vss
• Part Number Example: MT5C2565DJ-15 L
NOTE: Not all combinations of operating temperature, speed, data retention
and low power are necessarily available. Please contact the factory for availabil-
ity of specific part number combinations.
GENERAL DESCRIPTION
The MT5C2565 is organized as a 65,536 x 4 SRAM using
a four-transistor memory cell with a high-speed, low-power
CMOS process. Micron SRAMs are fabricated using double-
layer metal, double-layer polysilicon technology.
For flexibility in high-speed memory applications,
Micron offers chip enable (?C
/
E) and output enable (?O
/
E) with
this organization. These enhancements can place the out-
puts in High-Z for additional flexibility in system design.
Writing to these devices is accomplished when write
enable (?W
/
E) and
?
C
/
E inputs are both LOW. Reading is
accomplished when
?
W
/
E remains HIGH and
?
C
/
E and
?
O
/
E go
LOW. The device offers a reduced power standby mode
MT5C2565
Rev. 11/94
when disabled. This allows system designers to meet low
standby power requirements.
The “P” version provides a reduction in both operating
current (I
CC
) and TTL standby current (I
SB
1
). The latter is
achieved through the use of gated inputs on the
?
W
/
E,
?
O
/
E and
address lines, which also facilitates the design of battery
backed systems. That is, the gated inputs simplify the
design effort and circuitry required to protect against inad-
vertent battery current drain during power-down, when
inputs may be at undefined levels.
All devices operate from a single +5V power supply and
all inputs and outputs are fully TTL-compatible.
1
Micron Semiconductor, Inc., reserves the right to change products or specifications without notice.
©1994,
Micron Semiconductor, Inc.
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