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H5DU5162ETR-K3J

Description
DDR DRAM, 32MX16, 0.75ns, CMOS, PBGA60, ROHS COMPLIANT, FBGA-60
Categorystorage    storage   
File Size203KB,30 Pages
ManufacturerSK Hynix
Websitehttp://www.hynix.com/eng/
Environmental Compliance
Download Datasheet Parametric View All

H5DU5162ETR-K3J Overview

DDR DRAM, 32MX16, 0.75ns, CMOS, PBGA60, ROHS COMPLIANT, FBGA-60

H5DU5162ETR-K3J Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerSK Hynix
Parts packaging codeBGA
package instructionVBGA, TSSOP66,.46
Contacts60
Reach Compliance Codeunknown
ECCN codeEAR99
access modeFOUR BANK PAGE BURST
Maximum access time0.75 ns
Other featuresAUTO/SELF REFRESH
Maximum clock frequency (fCLK)133 MHz
I/O typeCOMMON
interleaved burst length2,4,8
JESD-30 codeR-PBGA-B60
JESD-609 codee6
length12 mm
memory density536870912 bit
Memory IC TypeDDR DRAM
memory width16
Number of functions1
Number of ports1
Number of terminals60
word count33554432 words
character code32000000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize32MX16
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeVBGA
Encapsulate equivalent codeTSSOP66,.46
Package shapeRECTANGULAR
Package formGRID ARRAY, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)260
power supply2.5 V
Certification statusNot Qualified
refresh cycle8192
Maximum seat height1 mm
self refreshYES
Continuous burst length2,4,8
Maximum standby current0.005 A
Maximum slew rate0.24 mA
Maximum supply voltage (Vsup)2.7 V
Minimum supply voltage (Vsup)2.3 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Bismuth (Sn/Bi)
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature20
width8 mm
512Mb DDR SDRAM
H5DU518(6)2ETR-xxC
H5DU518(6)2ETR-xxI
H5DU518(6)2ETR-xxL
H5DU518(6)2ETR-xxJ
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.1 / Aug. 2011
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