IBM11M4730C4M x 72 E12/10, 5.0V, Au.
IBM11N2645H
IBM11N2735H
2M x 64/72 DRAM MODULE
Features
• 168 Pin JEDEC Standard, Unbuffered 8 Byte
Dual In-line Memory Module
• 2Mx64, 2Mx72 Extended Data Out Page Mode
DIMM
S
• Performance:
-60
t
RAC
RAS Access Time
t
CAC
CAS Access Time
t
AA
t
RC
Access Time From Address
Cycle Time
60ns
15ns
30ns
-6R
60ns
17ns
30ns
-70
70ns
20ns
35ns
applications
• System Performance Benefits:
-Non buffered for increased performance
-Reduced noise (35 V
SS
/V
CC
pins)
-Byte write, byte read accesses
-Serial PDs
• Extended Data Out (EDO) Mode, Read-Modify-
Write Cycles
• Refresh Modes: RAS-Only, CBR and Hidden
Refresh
• 2048 refresh cycles distributed across 32ms
• 11/10 addressing (Row/Column)
• Card size: 5.25" x 1.0" x 0.157"
• DRAMS in TSOP Package
104ns 104ns 124ns
25ns
25ns
30ns
t
HPC
EDO Mode Cycle Time
• All inputs and outputs are LVTTL (3.3V) compat-
ible
• Single 3.3V
±
0.3V Power Supply
• Au contacts
• Optimized for byte-write non-parity, or ECC
Description
IBM11N2645H/IBM11N2735H are industry standard
168-pin 8-byte Dual In-line Memory Modules
(DIMMs) which are organized as 2Mx64 and 2Mx72
high speed memory arrays designed with EDO
DRAMs for non-parity or ECC applications. The
DIMMs use 8 (x64) or 9 (x72) 2Mx8 EDO DRAMs in
TSOP packages. The use of EDO DRAMs allows for
a reduction in Page Mode Cycle time from 40ns
(Fast Page) to 25ns (EDO, 60ns/6Rns sort).
The DIMMs use serial presence detects imple-
mented via a serial EEPROM using the two pin I
2
C
protocol. This communication protocol uses Clock
(SCL) and Data I/O (SDA) lines to synchronously
clock data between the master (system logic) and
the slave EEPROM device (DIMM). The EEPROM
device address pins (SA0-2) are brought out to the
DIMM tabs to allow 8 unique DIMM/EEPROM
addresses. The first 128 bytes are utilized by the
DIMM manufacturer and the second 128 bytes of
serial PD data are available to the customer.
All IBM 168-pin DIMMs provide a high performance,
flexible 8-byte interface in a 5.25” long space-saving
footprint. Related products include the buffered
DIMMs (x64, x72 parity and x72 ECC Optmized) for
applications which can benefit from the on-card buff-
ers.
Card Outline
(Front)
(Back)
1
85
10 11
94 95
40 41
124 125
84
168
50H7623
SA14-4634-03
Revised 5/96
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 30
IBM11N2645H
IBM11N2735H
2M x 64/72 DRAM MODULE
Pin Description
RAS0, RAS2
CAS0 - CAS7
WE0, WE2
OE0, OE2
A0 - A10
DQx
CBx
Row Address Strobe
Column Address Strobe
Read/write Input
Output Enable
Address Inputs
Data Input/Output
Check Bit Data Input/Output
V
CC
V
SS
NC
DU
SCL
SDA
SA0-2
Power (3.3V)
Ground
No Connect
Don’t Use
Serial Presence Detect Clock Input
Serial Presence Detect Data Input
Serial Presence Detect Address Inputs
Pinout
Pin#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Front
Side
V
SS
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
CC
DQ14
DQ15
CB0
Pin#
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
Back
Side
V
SS
DQ32
DQ33
DQ34
DQ35
V
CC
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
V
CC
DQ46
DQ47
CB4
Pin#
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Front
Side
CB1
V
SS
NC
NC
V
CC
WE0
CAS0
CAS1
RAS0
OE0
V
SS
A0
A2
A4
A6
A8
A10
NC
V
CC
V
CC
DU
Pin#
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
Back
Side
CB5
V
SS
NC
NC
V
CC
DU
CAS4
CAS5
NC
DU
V
SS
A1
A3
A5
A7
A9
NC
NC
V
CC
DU
DU
Pin#
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
Front
Side
V
SS
OE2
RAS2
CAS2
CAS3
WE2
V
CC
NC
NC
CB2
CB3
V
SS
DQ16
DQ17
DQ18
DQ19
V
CC
DQ20
NC
DU
NC
Pin#
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
Back
Side
V
SS
DU
NC
CAS6
CAS7
DU
V
CC
NC
NC
CB6
CB7
V
SS
DQ48
DQ49
DQ50
DQ51
V
CC
DQ52
NC
DU
NC
Pin#
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Front
Side
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
CC
DQ28
DQ29
DQ30
DQ31
V
SS
NC
NC
NC
SDA
SCL
V
CC
Pin#
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Back
Side
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
CC
DQ60
DQ61
DQ62
DQ63
V
SS
NC
NC
SA0
SA1
SA2
V
CC
Note:
All pin assignments are consistent for all 8 Byte Unbuffered versions.
Ordering Information
Part Number
IBM11N2645HB-60
IBM11N2645HB-6R
IBM11N2645HB-70
IBM11N2645HB-60T
IBM11N2645HB-6RT
IBM11N2645HB-70T
IBM11N2735HB-60
IBM11N2735HB-6R
IBM11N2735HB-70
IBM11N2735HB-60T
IBM11N2735HB-6RT
IBM11N2735HB-70T
2Mx72
2Mx64
Organization
Speed
60ns
6Rns
70ns
60ns
6Rns
70ns
60ns
6Rns
70ns
60ns
6Rns
70ns
2
2
2
1
11/10
Au
5.25”x1.0”x 0.157”
3.3V
2
2
2
1
Addr.
Leads
Dimension
Power
Notes
1. 6Rns speet sort has t
CAC
of 17ns.
2. DRAM package designator appended to speed portion of part number on assemblies beginning with DRAM die rev E.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H7623
SA14-4634-03
Revised 5/96
Page 2 of 30
IBM11N2645H
IBM11N2735H
2M x 64/72 DRAM MODULE
Truth Table
Function
Standby
Read
Early-Write
Late-Write
RMW
EDO Page Mode - Read 1st Cycle
Subsequent Cycles
EDO Page Mode - Write 1st Cycle
Subsequent Cycles
EDO Page Mode - RMW 1st Cycle
Subsequent Cycles
RAS-Only Refresh
CAS-Before-RAS Refresh
Read
Hidden Refresh
Write
Self Refresh
L→H→L
H→L
L
L
H
H
X
X
Row
X
Col
X
Data In
High Impedance
RAS
H
L
L
L
L
L
L
L
L
L
L
L
H→L
L→H→L
CAS
H→X
L
L
L
L
H→L
H→L
H→L
H→L
H→L
H→L
H
L
L
WE
X
H
L
H→L
H→L
H
H
L
L
H→L
H→L
X
H
H
OE
X
L
X
H
L→H
L
L
X
X
L→H
L→H
X
X
L
Row
Address
X
Row
Row
Row
Row
Row
N/A
Row
N/A
Row
N/A
Row
X
Row
Column
Address
X
Col
Col
Col
Col
Col
Col
Col
Col
Col
Col
N/A
X
Col
DQx
High Impedance
Valid Data Out
Valid Data In
Valid Data In
Valid Data In/Out
Valid Data Out
Valid Data Out
Valid Data In
Valid Data In
Valid Data In/Out
Valid Data In/Out
High Impedance
High Impedance
Data Out
Serial Presence Detect
SPD Entry
Byte #
0
1
2
3
4
5
6
7
8
9
Description
Number of SPD Bytes
Total # Bytes in Serial PD
Memory Type
# of Row Addresses
# of Column Addresses
# of DIMM Banks
Module Data Width
Module Data Width (Cont.)
Module Interface Levels
RAS Access
60ns
70ns
15ns
10
CAS Access
17ns
20ns
11
12
13
14
Dimm Config(Error Det/Corr.)
Refresh Rate/Type
Primary DRAM Organization
Secondary DRAM Organization
x64
x72
SPD Entry
Value
128
256
EDO
11
10
1
x64
x72
0
LVTTL
60
70
15
17
20
None
ECC
Normal 15.6
µs
Binary
Bit 7
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 6
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
Bit5
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
Bit4
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
Bit3
0
1
0
1
1
0
0
1
0
0
1
0
1
0
0
0
0
0
1
0
Bit2
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
0
0
0
0
0
Bit1
0
0
1
1
1
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
Bit0
0
0
0
1
0
1
0
0
0
1
0
0
1
1
0
0
0
0
0
0
Hex
80
08
02
0B
0A
01
40
48
00
01
3C
46
0F
11
14
00
02
00
08
00
x8
Undefined
50H7623
SA14-4634-03
Revised 5/96
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 5 of 30
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