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HM51W16400BLTS-8

Description
Fast Page DRAM, 4MX4, 80ns, CMOS, PDSO24, 0.300 INCH, PLASTIC, TSOP2-26/24
Categorystorage    storage   
File Size444KB,26 Pages
ManufacturerHitachi (Renesas )
Websitehttp://www.renesas.com/eng/
Download Datasheet Parametric View All

HM51W16400BLTS-8 Overview

Fast Page DRAM, 4MX4, 80ns, CMOS, PDSO24, 0.300 INCH, PLASTIC, TSOP2-26/24

HM51W16400BLTS-8 Parametric

Parameter NameAttribute value
MakerHitachi (Renesas )
Parts packaging codeTSOP2
package instructionTSOP2,
Contacts26
Reach Compliance Codeunknown
ECCN codeEAR99
access modeFAST PAGE
Maximum access time80 ns
Other featuresRAS ONLY/CAS BEFORE RAS/HIDDEN/SELF REFRESH
JESD-30 codeR-PDSO-G24
length17.14 mm
memory density16777216 bit
Memory IC TypeFAST PAGE DRAM
memory width4
Number of functions1
Number of ports1
Number of terminals24
word count4194304 words
character code4000000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize4MX4
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP2
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
Certification statusNot Qualified
Maximum seat height1.2 mm
self refreshYES
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
width7.62 mm
HM51W16400B Series
4,194,304-Word
×
4-Bit Dynamic Random Access Memory
ADE-203-368A (Z)
Rev. 1.0
Nov. 10, 1994
Description
The Hitachi HM51W16400B is a CMOS dynamic RAM organized 4,194,304-word
×
4-bit. It employs the
most advanced CMOS technology for high performance and low power. The HM51W16400B offers Fast
Page Mode as a high speed access mode.
Features
Single 3.3 V (±0.3 V)
High speed
Access time : 60 ns/ 70 ns/ 80 ns (max)
Low power dissipation
Active mode : 288 mW/252 mW/234 mW (max)
Standby mode : 7.2 mW (max)
: 0.36 mW (max) (L-version)
Fast page mode capability
Long refresh period
4096 refresh cycles : 64 ms
: 128 ms (L-version)
4 variations of refresh
RAS-only
refresh
CAS-before-RAS
refresh
Hidden refresh
Self refresh (L-version)
Test function
16-bit parallel test mode
Self refresh operation (L-version)
Battery backup operation (L-version)
This specification is fully compatible with the 16-Mbit DRAM specifications from TEXAS INSTRUMENTS.
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