K3N5C1000E-DC10 datasheet, PDF

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K3N5C1000E-DC10: DescriptionMASK ROM, 1MX16, 100ns, CMOS, PDIP42, 0.600 INCH, DIP-42; Categorystorage storage; File Size52KB，3 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

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K3N5C1000E-DC10 Overview

MASK ROM, 1MX16, 100ns, CMOS, PDIP42, 0.600 INCH, DIP-42

K3N5C1000E-DC10 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	SAMSUNG
Parts packaging code	DIP
package instruction	DIP, DIP42,.6
Contacts	42
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum access time	100 ns
Spare memory width	8
JESD-30 code	R-PDIP-T42
JESD-609 code	e0
length	52.42 mm
memory density	16777216 bit
Memory IC Type	MASK ROM
memory width	16
Number of functions	1
Number of terminals	42
word count	1048576 words
character code	1000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	1MX16
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP42,.6
Package shape	RECTANGULAR
Package form	IN-LINE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Certification status	Not Qualified
Maximum seat height	5.08 mm
Maximum standby current	0.00005 A
Maximum slew rate	0.05 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15.24 mm

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K3N5C1000E-D(G)C

16M-Bit (2Mx8 /1Mx16) CMOS MASK ROM

FEATURES

•

Switchable organization

2,097,152 x 8(byte mode)

1,048,576 x 16(word mode)

•

Fast access time

Random Access

100ns(Max.) : C

=50pF

120ns(Max.) : C

=100pF

•

Supply voltage : single +5V

•

Current consumption

Operating : 50mA(Max.)

Standby : 50µA(Max.)

•

Fully static operation

•

All inputs and outputs TTL compatible

•

Three state outputs

•

Package

-. K3N5C1000E-DC : 42-DIP-600

-. K3N5C1000E-GC : 44-SOP-600

CMOS MASK ROM

GENERAL DESCRIPTION

The K3N5C1000E-D(G)C is a fully static mask programmable

ROM fabricated using silicon gate CMOS process technology,

and is organized either as 2,097,152 x 8 bit(byte mode) or as

1,048,576 x 16 bit(word mode) depending on BHE voltage

level.(See mode selection table)

This device operates with a 5V single power supply, and all

inputs and outputs are TTL compatible.

Because of its asynchronous operation, it requires no external

clock assuring extremely easy operation.

It is suitable for use in program memory of microprocessor, and

data memory, character generator.

The K3N5C1000E-DC is packaged in a 42-DIP and the

K3N5C1000E-GC in a 44-SOP.

FUNCTIONAL BLOCK DIAGRAM

BUFFERS

AND

DECODER

PIN CONFIGURATION

MEMORY CELL

MATRIX

(1,048,576x16/

2,097,152x8)

42 A

41 A

40 A

39 A

38 A

37 A

36 A

35 A

34 A

33 A

32 BHE

N.C 1

44 N.C

43 A

42 A

41 A

40 A

39 A

38 A

37 A

36 A

35 A

34 A

33 BHE

32 V

31 Q

-1

30 Q

29 Q

28 Q

27 Q

26 Q

25 Q

24 Q

23 V

BUFFERS

AND

DECODER

SENSE AMP.

DATA OUT

BUFFERS

-1

BHE

CONTROL

LOGIC

. . .

CE 11

OE 13

DIP

Pin Name

- A

- Q

-1

BHE

N.C

Pin Function

Address Inputs

Data Outputs

Output 15(Word mode)/

LSB Address(Byte mode)

Word/Byte selection

Chip Enable

Output Enable

Power ( +5V)

Ground

No Connection

31 V

CE 12

30 Q

-1

29 Q

OE 14

28 Q

27 Q

26 Q

25 Q

24 Q

23 Q

22 V

SOP

K3N5C1000E-DC

K3N5C1000E-GC

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