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PUMD17

Description
Small Signal Bipolar Transistor
CategoryDiscrete semiconductor    The transistor   
File Size183KB,13 Pages
ManufacturerNexperia
Websitehttps://www.nexperia.com
Environmental Compliance
Download Datasheet Parametric Compare View All

PUMD17 Overview

Small Signal Bipolar Transistor

PUMD17 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerNexperia
package instructionSMALL OUTLINE, R-PDSO-G6
Reach Compliance Codecompliant
ECCN codeEAR99
Samacsys DescriptionTransistor NPN/PNP 50V 47K 22K SOT363 NXP, PUMD17 NPN+PNP Digital Transistor, 100 mA 50 V 47 kΩ, Ratio Of 2.13, 6-Pin UMT
Other featuresBUILT IN BIAS RESISTOR RATIO 2.68
Maximum collector current (IC)0.1 A
Collector-emitter maximum voltage50 V
ConfigurationSEPARATE, 2 ELEMENTS WITH BUILT-IN RESISTOR
Minimum DC current gain (hFE)60
JESD-30 codeR-PDSO-G6
JESD-609 codee3
Humidity sensitivity level1
Number of components2
Number of terminals6
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)260
Polarity/channel typeNPN AND PNP
surface mountYES
Terminal surfaceTin (Sn)
Terminal formGULL WING
Terminal locationDUAL
Maximum time at peak reflow temperature30
transistor applicationsSWITCHING
Transistor component materialsSILICON
Important notice
Dear Customer,
On 7 February 2017 the former NXP Standard Product business became a new company with the
tradename
Nexperia.
Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS
semiconductors with its focus on the automotive, industrial, computing, consumer and wearable
application markets
In data sheets and application notes which still contain NXP or Philips Semiconductors references, use
the references to Nexperia, as shown below.
Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/,
use
http://www.nexperia.com
Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use
salesaddresses@nexperia.com
(email)
Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on
the version, as shown below:
- © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights
reserved
Should be replaced with:
-
© Nexperia B.V. (year). All rights reserved.
If you have any questions related to the data sheet, please contact our nearest sales office via e-mail
or telephone (details via
salesaddresses@nexperia.com).
Thank you for your cooperation and
understanding,
Kind regards,
Team Nexperia

PUMD17 Related Products

PUMD17 PUMD17/T1 PUMD17/T2 PEMD17 934058922115
Description Small Signal Bipolar Transistor Small Signal Bipolar Transistor Small Signal Bipolar Transistor Small Signal Bipolar Transistor Small Signal Bipolar Transistor
Is it Rohs certified? conform to conform to conform to conform to conform to
Maker Nexperia Nexperia Nexperia Nexperia Nexperia
package instruction SMALL OUTLINE, R-PDSO-G6 SMALL OUTLINE, R-PDSO-G6 SMALL OUTLINE, R-PDSO-G6 SMALL OUTLINE, R-PDSO-F6 SMALL OUTLINE, R-PDSO-F6
Reach Compliance Code compliant compliant compliant compliant compliant
Other features BUILT IN BIAS RESISTOR RATIO 2.68 BUILT IN BIAS RESISTOR RATIO 2.68 BUILT IN BIAS RESISTOR RATIO 2.68 BUILT IN BIAS RESISTOR RATIO 2.68 BUILT IN BIAS RESISTOR RATIO 2.68
Maximum collector current (IC) 0.1 A 0.1 A 0.1 A 0.1 A 0.1 A
Collector-emitter maximum voltage 50 V 50 V 50 V 50 V 50 V
Configuration SEPARATE, 2 ELEMENTS WITH BUILT-IN RESISTOR SEPARATE, 2 ELEMENTS WITH BUILT-IN RESISTOR SEPARATE, 2 ELEMENTS WITH BUILT-IN RESISTOR SEPARATE, 2 ELEMENTS WITH BUILT-IN RESISTOR SEPARATE, 2 ELEMENTS WITH BUILT-IN RESISTOR
Minimum DC current gain (hFE) 60 60 60 60 60
JESD-30 code R-PDSO-G6 R-PDSO-G6 R-PDSO-G6 R-PDSO-F6 R-PDSO-F6
Number of components 2 2 2 2 2
Number of terminals 6 6 6 6 6
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE
Polarity/channel type NPN AND PNP NPN AND PNP NPN AND PNP NPN AND PNP NPN AND PNP
surface mount YES YES YES YES YES
Terminal form GULL WING GULL WING GULL WING FLAT FLAT
Terminal location DUAL DUAL DUAL DUAL DUAL
transistor applications SWITCHING SWITCHING SWITCHING SWITCHING SWITCHING
Transistor component materials SILICON SILICON SILICON SILICON SILICON
JESD-609 code e3 - - e3 e3
Humidity sensitivity level 1 - - 1 1
Peak Reflow Temperature (Celsius) 260 NOT SPECIFIED NOT SPECIFIED 260 -
Terminal surface Tin (Sn) - - Tin (Sn) Tin (Sn)
Maximum time at peak reflow temperature 30 NOT SPECIFIED NOT SPECIFIED 30 -

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