RDIMM
DDR2 SDRAM
DDR2 Registered SDRAM MODULE
240pin Registered Module based on 512Mb E-die
72-bit ECC
60FBGA with Lead-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE
CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-
WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL-
OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT
GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
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Rev. 1.4 August 2008
RDIMM
Table of Contents
DDR2 SDRAM
1.0 DDR2 Registered DIMM Ordering Information ..........................................................................4
2.0 Features ........................................................................................................................................4
3.0 Address Configuration ................................................................................................................4
4.0 Pin Configurations (Front side/Back side) ................................................................................5
5.0 Pin Description ............................................................................................................................5
6.0 Input/Output Functional Description .........................................................................................6
7.0 Functional Block Diagram ...........................................................................................................7
7.1 512MB, 64Mx72 Module - M393T6553EZ3/M393T6553EZA
.................................................................7
7.2 1GB, 128Mx72 Module - M393T2953EZ3/M393T2953EZA
....................................................................8
7.3 1GB, 128Mx72 Module - M393T2950EZ3/M393T2950EZA
...................................................................9
7.4 2GB, 256Mx72 Module - M393T5750EZ3/M393T5750EZA
..................................................................10
8.0 Absolute Maximum DC Ratings ................................................................................................11
9.0 AC & DC Operating Conditions ................................................................................................11
9.1 Recommended DC Operating Conditions (SSTL - 1.8)
.....................................................................11
9.2 Operating Temperature Condition
................................................................................................12
9.3 Input DC Logic Level
..................................................................................................................12
9.4 Input AC Logic Level
..................................................................................................................12
9.5 AC Input Test Conditions
............................................................................................................12
10.0 IDD Specification Parameters Definition ...............................................................................13
11.0 Operating Current Table : .......................................................................................................14
11.1 M393T6553EZ3 / M393T6553EZA : 512MB(64Mx8 *9) Module
.........................................................14
11.2 M393T6553EZ3 / M393T6553EZA : 512MB(64Mx8 *9) Module
.........................................................14
11.3 M393T2953EZ3 / M393T2953EZA : 1GB(64Mx8 *18) Module
...........................................................15
11.4 M393T2953EZ3 / M393T2953EZA : 1GB(64Mx8 *18) Module
...........................................................15
11.5 M393T2950EZ3 / M393T2950EZA : 1GB(128Mx4 *18) Module
.........................................................16
11.6 M393T2950EZ3 / M393T2950EZA : 1GB(128Mx4 *18) Module
.........................................................16
11.7 M393T5750EZ3 / M393T5750EZA : 2GB(128Mx4 *36) Module
.........................................................17
11.8 M393T5750EZ3 / M393T5750EZA : 2GB(128Mx4 *36) Module
.........................................................17
12.0 Input/Output Capacitance .......................................................................................................18
13.0 Electrical Characteristics & AC Timing for DDR2-800/667/533/400 .....................................18
13.1 Refresh Parameters by Device Density
........................................................................................18
13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
.............................................18
13.3 Timing parameters by speed grade (DDR2-800 and DDR2-667)
.......................................................19
13.4 Timing parameters by speed grade (DDR2-533 and DDR2-400)
.......................................................21
14.0 Physical Dimensions ...............................................................................................................23
14.1 64Mbx8 based 64Mx72 Module (1 Rank)
......................................................................................23
14.2 64Mbx8/128Mbx4 based 128Mx72 Module (2/1 Ranks)
...................................................................24
14.3 128Mbx4 based 256Mx72 Module (2 Ranks
) .................................................................................25
15.0 240 Pin DDR2 Registered DIMM Clock Topology .................................................................26
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Rev. 1.4 August 2008
RDIMM
Revision History
Revision
1.0
1.1
1.2
1.3
1.4
Month
April
May
June
July
August
Year
2007
2007
2007
2008
2008
- Initial Release
- Corrected Typo
- Corrected Typo
- Applied JEDEC update(JESD79-2E) on AC timing table
- VLP RDIMM specification is divided into the other datasheet
History
DDR2 SDRAM
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Rev. 1.4 August 2008
RDIMM
1.0 DDR2 Registered DIMM Ordering Information
Part Number
M393T6553EZ3-CD5/CC
M393T6553EZA-CF7/E6
M393T2953EZ3-CD5/CC
M393T2953EZA-CF7/E6
M393T2950EZ3-CD5/CC
M393T2950EZA-CF7/E6
M393T5750EZ3-CD5/CC
M393T5750EZA-CF7/E6
Density
512MB
512MB
1GB
1GB
1GB
1GB
2GB
2GB
Organization
64Mx72
64Mx72
128Mx72
128Mx72
128Mx72
128Mx72
256Mx72
256Mx72
Component Composition
64Mx8(K4T51083QE)*9EA
64Mx8(K4T51083QE)*9EA
64Mx8(K4T51083QE)*18EA
64Mx8(K4T51083QE)*18EA
128Mx4(K4T51043QE)*18EA
128Mx4(K4T51043QE)*18EA
128Mx4(K4T51043QE)*36EA
128Mx4(K4T51043QE)*36EA
Number of Rank
1
1
2
2
1
1
2
2
DDR2 SDRAM
Parity Register
X
O
X
O
X
O
X
O
Height
30.00mm
30.00mm
30.00mm
30.00mm
30.00mm
30.00mm
30.00mm
30.00mm
Note :
1. “Z” of Part number(11th digit) stands for Lead-Free products.
2. “3” of Part number(12th digit) stands for Dummy Pad PCB products.
3. “A” of Part number(12th digit) stands for Parity Register products.
2.0 Features
• Performance range
F7(DDR2-800)
Speed@CL3
Speed@CL4
Speed@CL5
Speed@CL6
CL-tRCD-tRP
-
533
667
800
6-6-6
E6(DDR2-667)
400
533
667
-
5-5-5
D5(DDR2-533)
400
533
533
-
4-4-4
CC(DDR2-400)
400
400
-
-
3-3-3
Units
Mbps
Mbps
Mbps
Mbps
CK
• JEDEC standard V
DD
= 1.8V ± 0.1V Power Supply
• V
DDQ
= 1.8V ± 0.1V
• 200 MHz f
CK
for 400Mb/sec/pin, 267MHz f
CK
for 533Mb/sec/pin, 333MHz f
CK
for 667Mb/sec/pin, 400MHz f
CK
for 800Mb/sec/pin
• 4 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5, 6
• Programmable Additive Latency: 0, 1 , 2 , 3, 4 and 5
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/Nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination with selectable values(50/75/150 ohms or disable)
• Average Refresh Period 7.8us at lower than a T
CASE
85°C, 3.9us at 85°C < T
CASE
< 95
°C
- Support High Temperature Self-Refresh rate enable feature
• Serial presence detect with EEPROM
• DDR2 SDRAM Package: 60ball FBGA - 128Mx4/64Mx8
• All of products are Lead-Free and RoHS compliant
Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.
3.0 Address Configuration
Organization
128Mx4(512Mb) based Module
64Mx8(512Mb) based Module
Row Address
A0-A13
A0-A13
Column Address
A0-A9,A11
A0-A9
Bank Address
BA0-BA1
BA0-BA1
Auto Precharge
A10
A10
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Rev. 1.4 August 2008
RDIMM
4.0 Pin Configurations (Front side/Back side)
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DDR2 SDRAM
Pin
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Front
V
REF
V
SS
DQ0
DQ1
V
SS
DQS0
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1
DQS1
V
SS
RESET
NC
V
SS
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2
DQS2
V
SS
DQ18
Back
V
SS
DQ4
DQ5
V
SS
DM0/DQS9
NC/DQS9
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1/DQS10
NC/DQS10
V
SS
RFU
RFU
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
DM2/DQS11
NC/DQS11
V
SS
DQ22
DQ23
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Front
DQ19
V
SS
DQ24
DQ25
V
SS
DQS3
DQS3
V
SS
DQ26
DQ27
V
SS
CB0
CB1
V
SS
DQS8
DQS8
V
SS
CB2
CB3
V
SS
V
DDQ
CKE0
V
DD
NC
NC/Err_Out
V
DDQ
A11
A7
V
DD
A5
Pin
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Back
V
SS
DQ28
DQ29
V
SS
DM3/DQS12
NC/DQS12
V
SS
DQ30
DQ31
V
SS
CB4
CB5
V
SS
DM8/DQS17
NC/DQS17
V
SS
CB6
CB7
V
SS
V
DDQ
CKE1
4
V
DD
NC
NC
V
DDQ
A12
A9
V
DD
A8
A6
Pin
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
Front
A4
V
DDQ
A2
V
DD
Pin
181
182
183
184
KEY
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
Back
V
DDQ
A3
A1
V
DD
CK0
CK0
V
DD
A0
V
DD
BA1
V
DDQ
RAS
S0
V
DDQ
ODT0
A13
V
DD
V
SS
DQ36
DQ37
V
SS
DM4/DQS13
NC/DQS13
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
V
SS
Pin
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Front
V
SS
DQS5
DQS5
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
SA2
NC(TEST)
V
SS
DQS6
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DQS7
DQS7
V
SS
DQ58
DQ59
V
SS
SDA
SCL
Pin
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Back
DM5/DQS14
NC/DQS14
V
SS
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
RFU
RFU
V
SS
DM6/DQS15
NC/DQS15
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DM7/DQS16
NC/DQS16
V
SS
DQ62
DQ63
V
SS
V
DDSPD
SA0
SA1
V
SS
V
SS
V
DD
NC/Par_In
V
DD
A10/AP
BA0
V
DDQ
WE
CAS
V
DDQ
S1
4
ODT1
V
DDQ
V
SS
DQ32
DQ33
V
SS
DQS4
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
NC = No Connect, RFU = Reserved for Future Use
1. RESET (Pin 18) is connected to both OE of PLL and Reset of register.
2. The Test pin (Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules (DIMMs)
3. NC/Err_Out ( Pin 55) and NC/Par_In (Pin 68) are for optional function to check address and command parity.
4. CKE1,S1 Pin is used for double side Registered DIMM.
5.0 Pin Description
Pin Name
CK0
CK0
CKE0, CKE1
RAS
CAS
WE
S0, S1
A0~A9, A11~A13
A10/AP
BA0, BA1
SCL
SDA
SA0~SA2
Par_In
Err_Out
RESET
Description
Clock Inputs, positive line
Clock inputs, negative line
Clock Enables
Row Address Strobe
Column Address Strobe
Write Enable
Chip Selects
Address Inputs
Address Input/Autoprecharge
DDR2 SDRAM Bank Address
Serial Presence Detect (SPD) Clock Input
SPD Data Input/Output
SPD address
Parity bit for the Address and Control bus
Parity error found in the Address and Control bus
Register and PLL control pin
Pin Name
ODT0~ODT1
DQ0~DQ63
CB0~CB7
DQS0~DQS8
DQS0~DQS8
DM(0~8),DQS(9~17)
DQS9~DQS17
RFU
NC
TEST
V
DD
V
DDQ
V
SS
V
REF
V
DDSPD
On die termination
Data Input/Output
Data check bits Input/Output
Data strobes
Data strobes, negative line
Data Masks / Data strobes (Read)
Data strobes (Read), negative line
Reserved for Future Use
No Connect
Memory bus test tool
(Not Connect and Not Useable on DIMMs)
Core Power
I/O Power
Ground
Input/Output Reference
SPD Power
Description
*The V
DD
and V
DDQ
pins are tied to the single power-plane on PCB.
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Rev. 1.4 August 2008
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