LinkSwitch-HP
Family
Energy Efficient, High-Power Off-Line Switcher
with Accurate Primary-Side Regulation (PSR)
Product Highlights
EcoSmart
™
- Energy Efficient
•
Multi-mode control maximizes efficiency over full load range
•
No-load consumption below 30 mW at 230 VAC (LNK67xx)
•
>75% efficiency with 1 W input at 230 VAC
•
>50% efficiency with 0.1 W input at 230 VAC
High Design Flexibility for Low System Cost
•
Dramatically simplifies power supply designs
•
Eliminates optocoupler and all secondary control circuitry
•
±5% or better output voltage tolerance
•
132 kHz operation reduces transformer and power supply size
•
Accurate programmable current limit
•
Compensation over line limits overload power
•
Frequency jittering reduces EMI filter cost
•
Fully integrated soft-start for minimum start-up stress
•
725 V MOSFET simplifies meeting derating requirements
(LNK677x)
•
650 V MOSFET for lowest system cost (LNK676x/LNK666x)
•
Fast transient response family option (LNK666x)
Extensive Protection Features
•
Auto-restart limits power delivery to 3% during overload faults
•
Output short-circuit protection (SCP)
•
Output overload/over-current protection (OPP, OCP)
•
Optional extended shutdown delay time
•
Output overvoltage protection (OVP), auto-restart or latching
•
Line brown-in/out protection (line UV)
•
Line overvoltage (OV) shutdown extends line surge withstand
•
Accurate thermal shutdown (OTP), hysteretic or latching
Advanced Green Package Options
•
eSIP
™
-7C package:
•
Vertical orientation for minimum PCB footprint
•
Simple heat sink mounting using clip or adhesive pad
•
eSOP
™
-12B package:
•
Low profile surface mounted for ultra-slim designs
•
Heat transfer to PCB via exposed pad and SOURCE pins
•
Supports either wave or IR reflow soldering
•
eDIP
™
-12B package:
•
Low profile through-hole mounted for ultra-slim designs
•
Heat transfer to PCB via exposed pad or optional metal heat sink
•
Extended creepage to DRAIN pin
•
Heat sink is connected to SOURCE for low EMI
•
Halogen free and RoHS compliant
Typical Applications
•
LCD Monitor and TV
•
Adapter
•
Appliances
•
Embedded power supplies (DVD, set-top box)
•
Industrial
CONTROL
Figure 1.
Typical Application Schematic.
Exposed
Pad
Exposed
Pad
eSIP-7C (E Package)
Figure 2.
Package Options.
eSOP-12B (K Package)
eDIP-12B (V Package)
Output Power Table
230 VAC ±15%
Product
4
85-265 VAC
Adapter
9W
12 W
13 W
11 W
15 W
20 W
13 W
18 W
26 W
15 W
22 W
40 W
19 W
27 W
55 W
21 W
30 W
63
3
W
25 W
36 W
72
3
W
Open
Frame
15 W
21 W
27 W
20 W
28 W
36 W
22 W
31 W
45 W
26 W
37 W
68
3
W
30 W
43 W
90
3
W
34 W
48 W
104
3
W
39 W
56 W
118
3
W
Heat Sink
PCB-W
1
PCB-R
2
Metal
PCB-W
1
PCB-R
2
Metal
PCB-W
1
PCB-R
2
Metal
PCB-W
1
PCB-R
2
Metal
PCB-W
1
PCB-R
2
Metal
PCB-W
1
PCB-R
2
Metal
PCB-W
1
PCB-R
2
Metal
Adapter
15 W
21 W
21 W
16 W
22 W
30 W
19 W
26 W
40 W
21 W
30 W
60 W
25 W
36 W
85
3
W
29 W
41 W
98
3
W
33 W
47 W
111
3
W
LNK6xx3K/V
LNK6xx3K
LNK6xx3E
LNK6xx4K/V
LNK6xx4K
LNK6xx4E
LNK6xx5K/V
LNK6xx5K
LNK6xx5E
LNK6xx6K/V
LNK6xx6K
LNK6xx6E
LNK6xx7K/V
LNK6xx7K
LNK6xx7E
LNK6xx8K/V
LNK6xx8K
LNK6xx8E
LNK6xx9K/V
LNK6xx9K
LNK6xx9E
Open
Frame
25 W
35 W
35 W
28 W
39 W
47 W
30 W
42 W
59
3
W
34 W
48 W
88
3
W
41 W
59 W
117
3
W
47 W
68 W
135
3
W
54 W
77 W
153
3
W
Table 1. Output Power Table.
Notes:
1. PCB heat sink with wave soldering.
2. PCB heat sink with IR reflow soldering (exposed pad thermally connected to PCB).
3. Maximum power specified based on proper thermal dissipation.
4. Packages: E: eSIP-7C, K: eSOP-12B, V: eDIP-12B. See Table 2 for all device options.
June 2015
www.power.com
This Product is Covered by Patents and/or Pending Patent Applications.
LinkSwitch-HP
BYPASS
(BP)
LATCH/HYSTERETIC
5.75 V
REGULATOR
DRAIN
(D)
THERMAL
SHUTDOWN
FAULT FILTER
5.75 V
4.9 V
+
-
BYPASS
PROGRAM
COMPENSATION
(CP)
MULTI-CYCLE
MODE CONTROL
MCM
OV
AUTO-
RESTART
OUTPUT
OVERVOLTAGE
AUTO-RESTART
HIGH GAIN
TRANS-
CONDUCTANCE
AMPLIFIER
AMP
ERROR
VOLTAGE
2V
REFERENCE
VOLTAGE
FEEDBACK
(FB)
+
SOFT-
START
S/H
LUV
LOV
GATE
DRIVER
LINE OVERVOLTAGE/
UNDERVOLTAGE
DETECTION
LINE
COMP
PROGRAM/
DELAY
(PD)
LINE
COMPENSATION
CUSTOM
SHUTDOWN
DELAY
PROGRAM
I
LIM
40% ~ 100%
CURRENT
LIMIT
SETTING
Figure 3.
Block Diagram.
LNK
Part Number
LNK6663E/K/V
LNK6664E/K/V
LNK6665E/K/V
LNK6666E/K/V
LNK6667E/K/V
LNK6668E/K/V
LNK6669E/K/V
LNK6763E/K/V
LNK6764E/K/V
LNK6765E/K/V
LNK6766E/K/V
LNK6767E/K/V
LNK6768E/K/V
LNK6769E/K/V
LNK6773E/K/V
LNK6774E/K/V
LNK6775E/K/V
LNK6776E/K/V
LNK6777E/K/V
LNK6778E/K/V
LNK6779E/K/V
6
Series
X
T
MCM(OFF)2
, 6 = 0.5 ms
7 = 4.0 ms
0.5 ms
0.5 ms
0.5 ms
0.5 ms
0.5 ms
0.5 ms
0.5 ms
4.0 ms
4.0 ms
4.0 ms
4.0 ms
4.0 ms
4.0 ms
4.0 ms
4.0 ms
4.0 ms
4.0 ms
4.0 ms
4.0 ms
4.0 ms
4.0 ms
BV
DSS1
, 6 = 650 V
7 = 725 V
650 V
650 V
650 V
650 V
650 V
650 V
650 V
650 V
650 V
650 V
650 V
650 V
650 V
650 V
725 V
725 V
725 V
725 V
725 V
725 V
725 V
6
Table 2.
Device Part Numbers and Options.
Notes:
1. Minimum breakdown voltage at T
J
= +25
°C.
2. T
MCM(OFF)
= 0.5 ms for fastest transient response, T
MCM(OFF)
= 4 ms for <30 mW no-load input power.
2
Rev. E 06/15
+
CLOCK
OSC
DC
MAX
OSCILLATOR
S
R
Q
Q
LEB
+
CURRENT LIMIT
COMPARATOR
PI-6565-072012
SOURCE
(S)
X
X
Power
E/V/K
Packages
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
Device
Size
www.power.com
LinkSwitch-HP
Pin Functional Description
BYPASS (BP) Pin:
An external bypass capacitor is connected to this pin for the
internally generated 5.75 V supply. Based on the connected
capacitance determined at start-up, it will provide either
auto-restart or latching shutdown option dependant on the fault
condition. Please see Table 3.
COMPENSATION (CP) Pin:
This pin is the output of transconductance amplifier. An RC
compensation network on this pin provides control loop
compensation.
DRAIN (D) Pin:
This pin is the high-voltage power MOSFET drain connection.
It also provides internal operating current for start-up until
output is in regulation.
FEEDBACK (FB) Pin:
The FEEDBACK pin is used to sense output and input voltage
by sensing the auxiliary winding voltage. During MOSFET
on-time, the current out of the FEEDBACK pin is sensed to
detect the line voltage. During the secondary rectifier
conduction time, the feedback voltage is proportional to the
output voltage via the turns ratio between the bias and
secondary windings.
PROGRAM (PD) Pin:
This MULTI-FUNCTIONAL pin sets device current limit and
optional shutdown delay time extension. During start-up, the
internal circuit decodes the current limit based on resistor loaded
on the PROGRAM pin. Please see Table 4. It can also be used
for optionally extending shutdown delay time by changing the
capacitance on the pin. See Figure 6.
SOURCE (S) Pin:
This pin is the power MOSFET source connection. It is also the
ground reference for the BYPASS, FEEDBACK, PROGRAM and
COMPENSATION pins.
Functional Description
A LinkSwitch™-HP device monolithically integrates a controller
and high-voltage power MOSFET into one package. It has a
newly developed analogue control scheme, which enables
continuous conduction mode (CCM), primary side regulated
(PSR) power supplies up to 90 W without the efficiency
limitation of DCM or audible noise. It uses an enhanced peak
current mode PWM control scheme with multi-mode operation.
The multi-mode control engine uses the error amplifier output
signal voltage at the COMPENSATION pin to set the operating
peak current and switching frequency to maintain the output
voltage in regulation as shown in Figure 5. For COMPENSATION
pin voltages lower than V
C(MCM)
(typ. 1.25 V) the device enters
multi-cycle modulation (MCM) with a fixed peak current of 25%
of the programmed current limit. Several innovative improvements
have been added to the peak current mode control to allow
primary side regulated CCM operation with no instability. The
device meets less than 30 mW input power with no-load at
high-line (LNK67xx families).
It also offers extensive built-in features:
•
External current limit selection.
•
Optional programmable shutdown delay time extension.
•
Optional remote On/Off.
•
Optional fast AC reset.
•
Primary-side sensed output overvoltage protection (OVP) .
•
Lost regulation protection during output overload or
short-circuit (auto-restart).
•
Internal current limit over line compensation for constant
overload power over line.
•
High-voltage bus overvoltage sense (line OV) for extended line
surge withstand.
•
High-voltage bus undervoltage sense (line UV) for brown-in/
out protection.
•
Accurate over-temperature protection (OTP).
•
Output OVP/OCP/OTP shutdown type selection (hysteretic/
latching).
•
Optional external latching shutdown input (current threshold)
•
Cycle-by-cycle current limit control.
Regulator/Shunt Voltage Clamp
The internal 5.75 V regulator charges the bypass capacitor
connected to the BYPASS pin to 5.75 V by drawing a current
from DRAIN whenever the power MOSFET is off. When the
power MOSFET is on, the device operates from the energy
stored in the bypass capacitor. In addition, there is a shunt
regulator clamping the bypass at 6.4 V when supply current is
provided by a bias winding through an external resistor. This
makes the device insensitive to bias winding voltage variations.
E Package
(eSIP-7C)
Exposed Pad
(Hidden)
Internally
Connected to
SOURCE Pin
Exposed Pad Internally
Connected to SOURCE Pin
V Package
(eDIP-12B)
1 PD
2 FB
3 CP
4 BP
6D
K Package
(eSOP-12B)
12 S
11 S
10 S
9S
8S
7S
PI-6564-081412
S 12
12345 7
P F CB S D
DBP P
S 11
S 10
S9
S8
S7
Exposed Pad (On Bottom)
Internally Connected to
SOURCE Pin
PD 1
FB 2
CP 3
BP 4
D6
Figure 4.
Pin Configuration.
3
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Rev. E 06/15
LinkSwitch-HP
current limit in less than time t
ON(SOA)
. This prevents excessive
drain currents during start-up and output short-circuit conditions
by providing additional time for the primary inductance to reset.
The SOA protection is disabled when the output voltage is
within 7.5% of regulation voltage.
Sample and Hold (S/H)
The sample and hold block senses the output voltage at auxiliary
winding during secondary rectifier on-time. The FEEDBACK pin
voltage is sampled after the turn-off of the internal switch to
compensate for diode conduction time differences. Sampling
time increases monotonically from 1.2
ms
at no or light load to
2.5
ms
at full load. Sampled voltage is held until the next clock
cycle. The output of S/H is fed to the error amplifier, once in
regulation the sampled voltage is 2 V.
BYPASS (BP) Programming
This feature selects either hysteretic or latching OVP/OCP and
OTP protection based on capacitor loading on the BYPASS pin.
The shutdown type is determined at the device power-up as
shown in Table 3.
C
BP
OVP
Lost Regulation
(SC, OC)
OTP
Table 3.
132
f
SW(LF)
Frequency (kHz)
32
Normalized Peak Current
Compensation
Voltage (∝ P
OUT
)
100%
50%
25%
V
C(MIN)
V
C(MCM)
V
C(MAX)
Compensation
Voltage (∝ P
OUT
)
PI-6722-111212
Figure 5.
Compensation Pin Characteristics (Multi-Mode Operation).
0.47
mF
Latching
4.7
mF
Auto-Restart
47
mF
Latching
Latching
Latching
Auto-Restart
In the event of an open-loop fault (no connection between the
feedback winding and the feedback divider network or the
FEEDBACK pin to the feedback network), the sensed current
out of FEEDBACK pin will be zero during MOSFET on-time, the
device enters into line brown-out protection (line UV). In the
event of output short-circuit or overload condition, the device
enters into auto-restart mode. Auto-restart minimizes the
power dissipation under fault conditions, the device will turn on
and off at duty cycle of typically 3% as long as the fault condition
persists. In auto-restart switching is disabled for t
AR(OFF)1
(typ. 150 ms) when the FEEDBACK pin voltage has dropped
below the auto-restart threshold V
FB(AR)
for the shutdown default
delay time t
AR(ON)
(typ. 35 ms). After this period switching is
enabled again with the device entering soft-start (typ. 15 ms).
For the first auto-restart off-period switching is disabled for a
reduced time t
AR(OFF)2
(typ. 1500 ms) to reduce the power supply
restart time during line cycling. Optionally the default shutdown
delay time can be extended by adding a capacitor to the
PROGRAM pin.
Hysteretic Thermal Shutdown
The thermal shutdown circuitry senses the controller die
temperature. The threshold is set at 142
°C
with a 75
°C
hysteresis (both typical). Once the device temperature rises
above 142
°C,
the power MOSFET is disabled and remains
disabled until the die temperature falls by 75
°C,
at which point
the device is re-enabled. The large hysteresis maintain the
average temperature below the temperature rating of low cost
CEM type PCB material in most cases.
Safe Operating Area (SOA) Protection
The device features a safe operating area (SOA) protection
mode which disables MOSFET switching for 4 consecutive
cycles in the event the peak switching current reaches the
Auto-Restart Auto-Restart
Latching
Hysteretic
Shutdown Type vs. Value of BYPASS Pin Capacitance.
Current Limit Setting
During power-up the cycle-by-cycle current limit is determined
by measuring the resistor value connected to the PROGRAM
pin by the measurement is performed by applying 1.25 V (see
Figure 10). The current limit can be set between 40% to 100%
in steps of 10% as shown in Table 4. After the current limit is
set the PROGRAM pin voltage is reduced to ~0 in order to
minimize power dissipation.
I
PD
mA
10
16
24
36
Table 4.
R
PD
kW
124
78.7
52.3
34.8
I
LIMIT(NORM)
%
100
90
80
70
I
PD
mA
54
83
125
R
PD
kW
23.2
15.0
10.0
I
LIMIT(NORM)
%
60
50
40
Current Limit Selection vs. Program Pin Resistor Value.
Programmable Shutdown Delay
The default auto-restart shutdown delay time t
SD(AR)
(typ. 35 ms)
can optionally be extended by connecting a capacitor to the
PROGRAM pin. Once a lost regulation fault is detected the
PROGRAM pin voltage is cycled 128 times between V
PD(DL)
(typ. 0.5 V) and V
PD(DU)
(typ. 1.2 V) as shown in Figure 10.
Figure 6 depicts the relationship between extended shutdown
delay time, added PROGRAM pin capacitor and current limit
programming resistor.
4
Rev. E 06/15
www.power.com
LinkSwitch-HP
Remote On/Off and Fast AC Reset
The PROGRAM pin can be used to turn on/off the device
remotely. If the voltage on the pin is set to 1.35 V externally, the
device stops switching. After releasing the PROGRAM pin the
PROGRAM pin device commences switching when the voltage
drops below 0.535 V.
At power-up the current out of the FEEDBACK pin has to
exceed the line undervoltage turn-on threshold (brown-in)
current I
FB(UVREF)
= -250
mA
(typ.) before switching is enabled.
During normal operation switching is disabled if the FEEDBACK
pin current falls below the line undervoltage turn-off threshold
(brown-out) current I
FB(UVOFF)
= -100
mA
(typ.) for at least 8
consecutive switching cycles. After switching has ended, the
device enters auto-restart. The applicable auto-restart off-
period t
AR(OFF)1
= 150 ms (typ.).
Auto-Restart On-Time Extension (ms)
450
400
350
300
250
200
150
100
50
0
1
PROGRAM Pin Resistor Value
124 kΩ
78.7 kΩ
52.3 kΩ
34.8 kΩ
23.2 kΩ
15.0 kΩ
10.0 kΩ
PI-6646-040412
500
V
BUS
N
P
V
SEC
N
S
D
C
O
V
O
N
A
D
BP
CONTROL
FB
T1
V
AUX
R
FB1
10
100
U1
S
PD
CP
PROGRAM Pin Capacitor Value (nF)
Figure 6.
Optional Shutdown Time Extension Programming.
V
FB
R
FB2
The PROGRAM pin can also be used to reset the device latch
after a latching OVP or OTP event. If the voltage on the pin is
set to 3.4 V externally, the device latch is reset. Once the
voltage drops below 0.535 V, device will start switching.
PI-6721-040412
PI-6837-120312
Figure 8.
Indirect High-Voltage Bus Sensing.
Normalized Set Current Limit (%)
110
Switching is also stopped if the FEEDBACK pin current exceeds
the line overvoltage threshold current I
FB(OV)
= -1.15 mA (typ.) for
at least 2 consecutive switching cycles.
Current Limit Compensation Over Line
The high-voltage bus is sensed by means of measuring the
current out of the FEEDBACK pin during the MOSFET on-time.
To limit available overload power over line the set current limit is
compensated as shown in Figure 7. The compensation is
disabled at peak currents below 50% of the set current limit,
and is re-enabled at 62.5% of the set current limit.
Soft-Start
A digital soft-start is implemented to reduce component stress
at power supply start-up. The internal reference voltage will ramp
up to 2 V during t
SOFT
(typ. 15 ms) at start-up. The loop will
typically close (output reaches regulation) during this time to
ensure smooth output voltage rise.
Fault Filter
This is the digital filter to handle all the fault conditions including
line overvoltage, line undervoltage, output overvoltage, and
output undervoltage, thermal shutdown as well as package
level fault (pin open-circuit or pin-to-pin short-circuit).
Transconductance Amplifier
The controller uses a high gain (typ. 70 dB) transconductance
amplifier to ensure exceptional output regulation.
100
90
80
70
-150
-300
-450
-600
-750
-900
-1050
-1200
FEEDBACK Pin Current During MOSFET On-Time
Figure 7.
Current Limit Compensation Over Line.
High-Voltage Bus Sensing
LinkSwitch-HP senses indirectly the HV voltage bus V
BUS
during
the power MOSFET on-time by monitoring the current flowing
out of the FEEDBACK pin. During the MOSFET on-time the
voltage across the auxiliary winding is proportional to the voltage
across the input winding. The current flowing through resistor
R
FB1
(see Figure 8) is therefore representing V
BUS
. Indirect line
sensing minimizes power dissipation and is used for line UV or
line OV protection and current limit compensation over line.
5
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Rev. E 06/15
FPGA/CPLD
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